From patchwork Thu Nov 26 08:31:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 332933 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1128392ilb; Thu, 26 Nov 2020 00:33:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJzSxQrjJTXLdHn4iIf+iZHCpdQNaEEEcYSCCbfsSeV4DkJMxoBJW6ECl3+PwS0psE0j/6nr X-Received: by 2002:a17:906:3648:: with SMTP id r8mr1632484ejb.145.1606379600339; Thu, 26 Nov 2020 00:33:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606379600; cv=none; d=google.com; s=arc-20160816; b=hjR+QfFkS5h0XtBKrg2yrw+s3N/sPi8j4nUEP0qcS5rHqFug2XIpu41T4zAha6bkNm mSAGJe3OqnQwedgC5T5n21Gx9DRdDXwvBdlrZd+THDBUpyHqWofGHQFYnqlL85P+fMyq Wb3w0+LhqgubEG16ept7C0Yb9QgnX5Rthkvu4N2fQ+Xg6oJrh+8UwPgk7p6CwlYyR2Di iO2kuwns0ZqvvM47mWw8jEOXWfV7WuEQGNHpR3GvrqRknfiAS04Pw8O9Lp3azgcddItu HoRVhrluLcagrxPfjhxbozCJijbHid8zAu0qmK54jafqHnczxvkrfhRNvQ8c6oIGii+c bqZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oRuYHyxqXzpChYy7W0ymMwWXMo0FUq8G8eMX6y4JimA=; b=KspxHc1xtZ9j/q9VYPT6oZS5YsPQVg+1vSVFKtHN2+izJzfxmyFQ1JVPhDR1asnkrE suiXJ/8Ant3OKR7VNsbw8lJQMZCxBhnEMB6yHGSTxr7/iYHW/7fUSR0klnFUYvaioycI 0oEHdfyPZJ/kIqX+YtH0sVQvOZFe1v80fvZxETATvXNCw/CVsJkVNtXoFC2g64bND123 tIBIP4mpPFzJdEcPad8q6PzN8dXXloZGSVD2Xuh/HWo87xV2LSaZaAad3XeRNXcYxDFM sIbH+gfP1e5TnbXY5LLAR8ZcgHICrkfm7WgS+5Vft3RqaWGfWuhCajr54eb0DmY4+KCC EM7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yt66b2fG; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m6si2722631eji.658.2020.11.26.00.33.20; Thu, 26 Nov 2020 00:33:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yt66b2fG; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388967AbgKZIb5 (ORCPT + 15 others); Thu, 26 Nov 2020 03:31:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728795AbgKZIb5 (ORCPT ); Thu, 26 Nov 2020 03:31:57 -0500 Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47B68C0613D4 for ; Thu, 26 Nov 2020 00:31:57 -0800 (PST) Received: by mail-pf1-x442.google.com with SMTP id b63so983367pfg.12 for ; Thu, 26 Nov 2020 00:31:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oRuYHyxqXzpChYy7W0ymMwWXMo0FUq8G8eMX6y4JimA=; b=yt66b2fGthFIztxfIKA0VR66dgzmwk7nMhiLSxEobLV8wX+l9OSBkcpx5Onm8na6IJ G/3Z/M+porRIba9qq4uDXTJW+igSJ9ut7GzXgnlkquRtgbzX3n9uopbHzaY9i2jXNXwH jank50avNR1qdDwbDsu0GhE5oyBOfaXjUER2JuRPt53DFeZ5oIETf+qPIG5S3MdgDFMI 6bIeHWr8eKIuKCP3F//jFlr9PnMZVd2MQLaPdrLGK5hn3LD209trezNKESZwJbxh43bQ KInLjkSOffzH/cmdJ5SSbZTOJP//5itBry76RvdXNdDdMVjtUWVNgiXRPH+XcevB+a6X Q0HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oRuYHyxqXzpChYy7W0ymMwWXMo0FUq8G8eMX6y4JimA=; b=UYUjHnJJnRtjkUVOD6akaUuXfbfhpuVfzvFx9dD4mZhOs8cXO4HH/+NDZiztYk6E7b zgCIzh2Qw/5ZCU5XLMNttBK0i9Eav8b3WDHDJP+Ipno0niPYardG5P5Tn4mnb0wiols0 cqQRgbpg8BReV7dgAYRP2tdWa/MbpXzA1SfmsBOcdEIVyme1ZKkyu9Rj4PK8FSjiUNFk v9y1ME2Meerc34zmpfItUg78U7di36ITRUrtJAMLp+4l7av/7gl/v0gU1kmdI3KjvkE4 kumaDm9nixD3dc68nb7m1XdEf6oVWPRfNWMLxO25PW18wLZJQycgc2wuSfPqT6eBvNU9 RYdw== X-Gm-Message-State: AOAM5308hXhhXn+IKKsNUM2Fd/nbO4GPOqRcKE02FHQlvwyp7juuYAI2 oGtD56QT04N4HR281Q7yyWe1 X-Received: by 2002:a17:90a:66c7:: with SMTP id z7mr2415427pjl.175.1606379516823; Thu, 26 Nov 2020 00:31:56 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6e95:f2a:3996:9d7f:e389:7f7d]) by smtp.gmail.com with ESMTPSA id b21sm5360949pji.24.2020.11.26.00.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Nov 2020 00:31:56 -0800 (PST) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: vkoul@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 2/2] ARM: dts: qcom: Add SDX55 platform and MTP board support Date: Thu, 26 Nov 2020 14:01:38 +0530 Message-Id: <20201126083138.47047-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201126083138.47047-1-manivannan.sadhasivam@linaro.org> References: <20201126083138.47047-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add basic devicetree support for SDX55 platform and MTP board from Qualcomm. The SDX55 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Currently, this basic devicetree support includes GCC, RPMh clock, INTC and Debug UART. Co-developed-by: Vinod Koul Signed-off-by: Vinod Koul Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 27 ++++ arch/arm/boot/dts/qcom-sdx55.dtsi | 193 +++++++++++++++++++++++++++ 3 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-sdx55-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-sdx55.dtsi -- 2.25.1 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..1505c6cdc5ca 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -917,7 +917,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974-sony-xperia-amami.dtb \ qcom-msm8974-sony-xperia-castor.dtb \ qcom-msm8974-sony-xperia-honami.dtb \ - qcom-mdm9615-wp8548-mangoh-green.dtb + qcom-mdm9615-wp8548-mangoh-green.dtb \ + qcom-sdx55-mtp.dtb dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts new file mode 100644 index 000000000000..262660e6dd11 --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +/dts-v1/; + +#include "qcom-sdx55.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX55 MTP"; + compatible = "qcom,sdx55-mtp", "qcom,sdx55"; + qcom,board-id = <0x5010008 0x0>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi new file mode 100644 index 000000000000..c236faf9726b --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX55 SoC device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdx55"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + blsp1_uart3: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x00831000 0x200>; + interrupts = ; + clocks = <&gcc 30>, + <&gcc 9>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + pdc: interrupt-controller@b210000 { + compatible = "qcom,sdx55-pdc", "qcom,pdc"; + reg = <0x0b210000 0x30000>; + qcom,pdc-ranges = <0 179 52>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = ; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = ; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = ; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = ; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = ; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = ; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = ; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17840000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x17830000 0x10000>, <0x17840000 0x10000>; + reg-names = "drv-0", "drv-1"; + interrupts = , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <1>; + qcom,tcs-config = , , + , ; + + rpmhcc: clock-controller { + compatible = "qcom,sdx55-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +};