| Message ID | 20201130093924.45057-3-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Accepted |
| Commit | 0085a33a25cc534838f801d697f87725e835743c |
| Headers | show |
| Series | Add LLCC support for SM8250 SoC | expand |
On 2020-11-30 15:09, Manivannan Sadhasivam wrote: > Add support for Last Level Cache Controller (LLCC) in SM8250 SoC. > This LLCC is used to provide common cache memory pool for the cores in > the SM8250 SoC thereby minimizing the percore caches. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi > b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 65acd1f381eb..118b6bb29ebc 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -1758,6 +1758,12 @@ usb_1_dwc3: dwc3@a600000 { > }; > }; > > + system-cache-controller@9200000 { > + compatible = "qcom,sm8250-llcc"; > + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; > + reg-names = "llcc_base", "llcc_broadcast_base"; > + }; > + > usb_2: usb@a8f8800 { > compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; > reg = <0 0x0a8f8800 0 0x400>; Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..118b6bb29ebc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1758,6 +1758,12 @@ usb_1_dwc3: dwc3@a600000 { }; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8250-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + usb_2: usb@a8f8800 { compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>;
Add support for Last Level Cache Controller (LLCC) in SM8250 SoC. This LLCC is used to provide common cache memory pool for the cores in the SM8250 SoC thereby minimizing the percore caches. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.25.1