From patchwork Tue Jan 5 12:26:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 356863 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15765523jai; Tue, 5 Jan 2021 04:31:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJw3PoZnSQwPeGc5M2sTgBXDISZvCp2+gONYAfWmZ8DO1q1NQ3gaxMhbFq0X0COAsQ8x2i69 X-Received: by 2002:a17:906:40d3:: with SMTP id a19mr68637624ejk.98.1609849876894; Tue, 05 Jan 2021 04:31:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609849876; cv=none; d=google.com; s=arc-20160816; b=Jb6k3d3HFHNMWFxtR6pZI8FdFSXVjR/Oug8qsxiDqKnE2hHSWrrfINjwS0QMDwaHww tQpAF5cwSqYIPVfpD50wYhoeKpAodAHzk20Manp6TuefpMdSHmfha43NWSANmO+Zx8MM WNPDLGZOXj3AsjahDi9VGdjxL67dfSNv8bB1tl5iY7GsSZ8ERQ2mnDUuy2isPyQKKaOA kHpLtRZZCFRbTqaQfQqdIi57WmQdCTn6dleb1jmtGhJLNs+YqHzyzGUrPzDjxwbIBzGa Bl7ZwaZ07NAtSW50UIZA/uuQdfnV/MaQUSMJIz/cad42tqnjdwg2cMdcR/yLNmlQsT0J AQ6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cts2vGZ7rrrSCXfEGOMmkzEVqPBhvajN3PzO1Zo1Cp8=; b=zDRMALpSZhIxSxohpgsP3Rd1oDhIRmomWnt2dQw12R9qxqhHulpmBSw+t7FRuE3eCt /SPaTo2JXhTTax5c7LDFt7LiKso+A/TZAvuZthYI6Y6Vdgff6WDYxIZZOgCApBFV+V2T 3OpSraWO44eEsEi40vp32C5ZLngetcuZGasobAF6dHAXCMvX1Slxgd8UZg9zPjasiyas 4Eg4jsQ914ILsAORYciJsR2W52d4cQqHnHZJDcQF+8bcjGBC/Nic44FyTw7E/CBvk1Br JU0HfYLctoAVfqISmku7+IHZJfU4Nkl4rSALfZheOn5xE7U3+aWjmoaq8Kd8NjHRgBvW FyGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="A/xhvNWQ"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i8si20352221edu.515.2021.01.05.04.31.16; Tue, 05 Jan 2021 04:31:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="A/xhvNWQ"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730226AbhAEMaS (ORCPT + 15 others); Tue, 5 Jan 2021 07:30:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730175AbhAEM2e (ORCPT ); Tue, 5 Jan 2021 07:28:34 -0500 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFD83C0617A9 for ; Tue, 5 Jan 2021 04:27:20 -0800 (PST) Received: by mail-pg1-x536.google.com with SMTP id c22so21142921pgg.13 for ; Tue, 05 Jan 2021 04:27:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cts2vGZ7rrrSCXfEGOMmkzEVqPBhvajN3PzO1Zo1Cp8=; b=A/xhvNWQghdZ1v4PRVIws+W+VCAoVlmPb91g7nE856rTTVBk+DFsEbuo4DcRau8oM4 a7oLHdOCsNCObQ2lipGXaeLP/skC1PSPxXifXTgWRcmDoQeICGve9jHgasfqpJugDrbY tyfoPNfDC0yzW5vONsqHlz3x762+pVhCAhPzErkFHWIjrzMn1q3kHyHCg2HpPdt1gNtB C33NzAEAI9QBA+pg1ZATo9/bPk6mAxhMZOO+DsQnmS7IEH8FfCXwqoeDPn3tJWE8rGO8 8p9A6zFR/J+YTur4LobVmzlyRw/D35GleVHABr38EmdyRWhMRgX05g9ZjJerE3r8usO8 JzgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cts2vGZ7rrrSCXfEGOMmkzEVqPBhvajN3PzO1Zo1Cp8=; b=Ny0JkqZffCdoMLfFHO6Vku00oSHlIu70x7gn4LCZp8GOdx7Pgu7KRvVRSgJNTDOuls Lr79X+NgVDtuSB/1QR7KMVLjo4brH38rQqB7zJjxkhz/MgccmMG6vX7oOvbf4rHeUMmo HG4q9zIY3la493F2U/vYzc0VQmwWyIHgteIyq0cl124pUWT+CMZrH9SqSIjsMO3axUlq ubj79eRnnbofiTSviIhWr02aWSufA9E3EgIUuTNmkOy+wra/Wwod/V7f6QCMoHrXW5Xn LKySYKHgVGYN8GxOWHyAJ5PC0N7IoKOnYi1Stcrw2nwlAod2o9shg70HE+bD1nP2S71r 3HvQ== X-Gm-Message-State: AOAM530/fqsqotGgcOKRwz0Ez9B1GPfebZtzKfGmv7qD1Vdz/98Nc+U8 X3yiNHFSTb9WcAyIWoMKJ8mYHlmzp6KY X-Received: by 2002:a63:1707:: with SMTP id x7mr42296314pgl.266.1609849640231; Tue, 05 Jan 2021 04:27:20 -0800 (PST) Received: from localhost.localdomain ([103.77.37.191]) by smtp.gmail.com with ESMTPSA id t22sm64745402pgm.18.2021.01.05.04.27.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 04:27:19 -0800 (PST) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 07/18] ARM: dts: qcom: sdx55: Add support for TCSR Mutex Date: Tue, 5 Jan 2021 17:56:38 +0530 Message-Id: <20210105122649.13581-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210105122649.13581-1-manivannan.sadhasivam@linaro.org> References: <20210105122649.13581-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX55 platform. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.25.1 Reviewed-by: Vinod Koul diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 927f43a7414c..e48ec7a1971b 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -166,6 +166,17 @@ sdhc_1: sdhci@8804000 { status = "disabled"; }; + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>;