From patchwork Fri Jan 15 03:16:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 364746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3E6BC433E9 for ; Fri, 15 Jan 2021 03:17:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D32123A9D for ; Fri, 15 Jan 2021 03:17:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732364AbhAODR0 (ORCPT ); Thu, 14 Jan 2021 22:17:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732359AbhAODR0 (ORCPT ); Thu, 14 Jan 2021 22:17:26 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD22CC0613C1 for ; Thu, 14 Jan 2021 19:16:45 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id b5so4403291pjl.0 for ; Thu, 14 Jan 2021 19:16:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hyxvs6de5u+Z0m5qJhr7VhYBFLTdTIfC8RRDwWALIGE=; b=HAbKDK5rv41PPGuh2wyV3MFE70eGf6mPnEf1NMLGeGm5JRHPpB+hLQ0wdNWXyhMPtb 1lSfZ3g9SzALttGKdtcHryzu9F9zSNz9l7pYqXWq5LskTDzwlHt0eDRHme0McQ0KPd/l FlkBqLs5lznTP1vC9juIYvp4WhILRV84VdIsc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hyxvs6de5u+Z0m5qJhr7VhYBFLTdTIfC8RRDwWALIGE=; b=nlMUWmOe8xpZ8MLH8YJ88xJ2hYQiEAJJ44wFDzmCLf11x8byZkPlqTlHm1VglpCewa M4drJmLpwXo46DsqTEL5D3ML5K0l13rqjmcTrcKHnz5o9eytPJD5k4Q4dhV04vmCIAKS FlBPD/+mMAl6HDNKDccMCUPQYYE+1v4eSf7U0cRBbQ6Bq6g6oEQJPDR2hhm3LtiPEqSj r7P+Zv9TyY9UQMLXUJx9nyfH7T3gPPEiEanIKoRvqKGEqP51yySJPBEIaW7pYS7WTLKY 3pu/CnTMQ6b+HYLZlfX0Z+uNYfbqweGh+RfjeX1vW2HkKhZjfLSJp25hgIdK4oU8CA3B tbhA== X-Gm-Message-State: AOAM533GVqteYfsaBohyp56Dh39YdlUfO/fiebkHGl9YTvx0uYCvLnOz KQcOwQF5QJiOyr4Sp2LTzWH+HcedvyqT/z+N X-Google-Smtp-Source: ABdhPJz/TOwL5g0bqm8zhaIK26fsyTXSQybdBfLWLSXM8nfDQ0sR5O5NUGxSTueSzAcyJf0vMtJh7g== X-Received: by 2002:a17:902:d50d:b029:de:5b13:498d with SMTP id b13-20020a170902d50db02900de5b13498dmr5498673plg.38.1610680605123; Thu, 14 Jan 2021 19:16:45 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:42b0:34ff:fe3d:58e6]) by smtp.gmail.com with ESMTPSA id q26sm6346318pfl.219.2021.01.14.19.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 19:16:44 -0800 (PST) From: Douglas Anderson To: Marc Zyngier , Thomas Gleixner , Jason Cooper , Linus Walleij Cc: Stephen Boyd , Neeraj Upadhyay , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Bjorn Andersson , Rajendra Nayak , Srinivas Ramana , Maulik Shah , Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH v7 1/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 Date: Thu, 14 Jan 2021 19:16:21 -0800 Message-Id: <20210114191601.v7.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid> X-Mailer: git-send-email 2.30.0.284.gd98b1dd5eaa7-goog MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There's currently a comment in the code saying function 0 is GPIO. Instead of hardcoding it, let's add a member where an SoC can specify it. No known SoCs use a number other than 0, but this just makes the code clearer. NOTE: no SoC code needs to be updated since we can rely on zero-initialization. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Maulik Shah Tested-by: Maulik Shah Reviewed-by: Bjorn Andersson --- (no changes since v6) Changes in v6: - Don't wrap line; bust through 80 columns! drivers/pinctrl/qcom/pinctrl-msm.c | 3 +-- drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index e051aecf95c4..d1261188fb6e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -210,8 +210,7 @@ static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, if (!g->nfuncs) return 0; - /* For now assume function 0 is GPIO because it always is */ - return msm_pinmux_set_mux(pctldev, g->funcs[0], offset); + return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); } static const struct pinmux_ops msm_pinmux_ops = { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 333f99243c43..e31a5167c91e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -118,6 +118,7 @@ struct msm_gpio_wakeirq_map { * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need * to be aware that their parent can't handle dual * edge interrupts. + * @gpio_func: Which function number is GPIO (usually 0). */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -134,6 +135,7 @@ struct msm_pinctrl_soc_data { const struct msm_gpio_wakeirq_map *wakeirq_map; unsigned int nwakeirq_map; bool wakeirq_dual_edge_errata; + unsigned int gpio_func; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;