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[01/15] ARM: dts: qcom: sdx55: Add support for A7 PLL clock

Message ID 20210408170457.91409-2-manivannan.sadhasivam@linaro.org
State Accepted
Commit 37f0f245f92a1fbb4786762129b7b1f090720a43
Headers show
Series SDX55 devicetree updates | expand

Commit Message

Manivannan Sadhasivam April 8, 2021, 5:04 p.m. UTC 
On SDX55 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

---
 arch/arm/boot/dts/qcom-sdx55.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

-- 
2.25.1
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Patch

diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index e4180bbc4655..41c90f598359 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -352,6 +352,14 @@  intc: interrupt-controller@17800000 {
 			      <0x17802000 0x1000>;
 		};
 
+		a7pll: clock@17808000 {
+			compatible = "qcom,sdx55-a7pll";
+			reg = <0x17808000 0x1000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <0>;
+		};
+
 		watchdog@17817000 {
 			compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
 			reg = <0x17817000 0x1000>;