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[88.207.99.66]) by smtp.googlemail.com with ESMTPSA id w14sm13511513edj.6.2021.05.18.10.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 10:51:57 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, speriaka@codeaurora.org, sivaprak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH] clk: qcom: ipq8074: fix PCI-E clock oops Date: Tue, 18 May 2021 19:51:53 +0200 Message-Id: <20210518175153.3176764-1-robimarko@gmail.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix PCI-E clock related kernel oops that are causes by missing parent_names. Without the use of parent_names kernel will panic on clk_core_get_parent_by_index() due to a NULL pointer. Without this earlycon is needed to even catch the OOPS as it will reset the board before serial is initialized. Fixes: f0cfcf1ade20 ("clk: qcom: ipq8074: Add missing clocks for pcie") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 0c619ed35c82..8d8b1717a203 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4357,8 +4357,7 @@ static struct clk_rcg2 pcie0_rchng_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie0_rchng_clk_src", - .parent_hws = (const struct clk_hw *[]) { - &gpll0.clkr.hw }, + .parent_names = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -4372,8 +4371,8 @@ static struct clk_branch gcc_pcie0_rchng_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie0_rchng_clk", - .parent_hws = (const struct clk_hw *[]){ - &pcie0_rchng_clk_src.clkr.hw, + .parent_names = (const char *[]){ + "pcie0_rchng_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -4390,8 +4389,8 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie0_axi_s_bridge_clk", - .parent_hws = (const struct clk_hw *[]){ - &pcie0_axi_clk_src.clkr.hw, + .parent_names = (const char *[]){ + "pcie0_axi_clk_src" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT,