From patchwork Fri Sep 3 23:24:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 507064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5095EC433EF for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C0A56112F for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350764AbhICXZc (ORCPT ); Fri, 3 Sep 2021 19:25:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350758AbhICXZa (ORCPT ); Fri, 3 Sep 2021 19:25:30 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5090C061764 for ; Fri, 3 Sep 2021 16:24:29 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id i28so1151096ljm.7 for ; Fri, 03 Sep 2021 16:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sghiWtzlQ2rh7GwVQZPgVNRESKtI3sTnOWU+E5ytGWY=; b=qel2ha5l98HDglOR7KVyNaIQV6oghHJprK7J0b/eW0gJALtdPnrjGtTZlaae1gL0U+ zhc4+Bpv5EsP+88w9WMWAmKL7Gy5SmygUiImm/t2l3Vlb0G8UVSvlWi+MYAyyJSXEzxz L0GnP476/FNq2ItPdX4RpOVkl8BUtAZF/vXYJrJxALptUGVy9u8gJFa2aM9gx2bWD3Yn cvVxa1Ch1BcLswqrIiuhpuRHaA1cKQp30CBV/yUiANUPXalNBcsgVPimbRfFwg1iljM+ 8VVs9Ue0ACefayagCcPPvN5as6nNbHY/n/MaAnXEYtnNSMedS9P8tCkizqNR9YQ0Wlkr dehg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sghiWtzlQ2rh7GwVQZPgVNRESKtI3sTnOWU+E5ytGWY=; b=jVgQM7Z6uD3Q3deiDT3SBnz393zuOnYm8ftxRQYNTO1k4Mlb9GlBMkiKDutJ36v2qj Cn/IOG47xVutJ0iAQnBScuk3noAo2J1u5JFbc5XD3wA8aXbbP7CAv0uJsbXI3K7gTCwW +YYN8pZka5FSdI7LvxqQtxs4XhJEp4iyGhLtX2wmBdOdZpEn0PDVecfNBKOctqxrzH2D Wix4atHvQsaK+thTNQ0lm/My39pueMvg6TJtWAcMCLMsiI69fMg5B1pzDbdY5HBM0HCS mcd40J9nQb/ac+7LLUulTGcVkneQ6TTibbgJ2TowcjqgJY/8XCJrdGTMOg+TnookO7hD UVog== X-Gm-Message-State: AOAM530xPJNTHanOTEEimiKJyiBYPNYdiCfl/te+UxYy+Lyic49vfTfo EKUuXQvKoMYN47V2WncciAYeFb0cgB+eMg== X-Google-Smtp-Source: ABdhPJz7hzfKas67Hx3clwBLUCMwQpaomk+7Uwg/sYd87Ekj8t6SP/fQP0iqQccJiOhLhmxPfAk5aQ== X-Received: by 2002:a2e:991a:: with SMTP id v26mr987286lji.111.1630711468129; Fri, 03 Sep 2021 16:24:28 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 05/11] interconnect: icc-rpm: add support for QoS reg offset Date: Sat, 4 Sep 2021 02:24:15 +0300 Message-Id: <20210903232421.1384199-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SDM660 driver expects to have QoS registers at the beginning of NoC address space (sdm660 platform shifts NoC base address). Add support for using QoS register offset, so that other platforms do not have to change existing device trees. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.c | 24 ++++++++++++++---------- drivers/interconnect/qcom/icc-rpm.h | 3 +++ 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index b8bac738c64f..384b571fffec 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -39,7 +39,7 @@ #define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) #define NOC_QOS_MODEn_MASK 0x3 -static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, +static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos, int regnum) { @@ -58,8 +58,8 @@ static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; } - return regmap_update_bits(rmap, - M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), mask, val); } @@ -84,7 +84,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw) */ if (mode != NOC_QOS_MODE_BYPASS) { for (i = 3; i >= 0; i--) { - rc = qcom_icc_bimc_set_qos_health(qp->regmap, + rc = qcom_icc_bimc_set_qos_health(qp, &qn->qos, i); if (rc) return rc; @@ -94,11 +94,12 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw) val = 1; } - return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port), M_BKE_EN_EN_BMASK, val); } -static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, +static int qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos) { u32 val; @@ -106,12 +107,14 @@ static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, /* Must be updated one at a time, P1 first, P0 last */ val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; - rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + rc = regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), NOC_QOS_PRIORITY_P1_MASK, val); if (rc) return rc; - return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), NOC_QOS_PRIORITY_P0_MASK, qos->prio_level); } @@ -140,7 +143,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) if (mode == NOC_QOS_MODE_FIXED) { dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", qn->name); - rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); + rc = qcom_icc_noc_set_qos_priority(qp, &qn->qos); if (rc) return rc; } else if (mode == NOC_QOS_MODE_BYPASS) { @@ -149,7 +152,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) } return regmap_update_bits(qp->regmap, - NOC_QOS_MODEn_ADDR(qn->qos.qos_port), + qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), NOC_QOS_MODEn_MASK, mode); } @@ -305,6 +308,7 @@ int qnoc_probe(struct platform_device *pdev) qp->num_clks = cd_num; qp->is_bimc_node = desc->is_bimc_node; + qp->qos_offset = desc->qos_offset; if (desc->regmap_cfg) { struct resource *res; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 868585c80f38..f6746dabdf28 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -18,6 +18,7 @@ * @bus_clks: the clk_bulk_data table of bus clocks * @num_clks: the total number of clk_bulk_data entries * @is_bimc_node: indicates whether to use bimc specific setting + * @qos_offset: offset to QoS registers * @regmap: regmap for QoS registers read/write access */ struct qcom_icc_provider { @@ -25,6 +26,7 @@ struct qcom_icc_provider { int num_clks; bool is_bimc_node; struct regmap *regmap; + unsigned int qos_offset; struct clk_bulk_data bus_clks[]; }; @@ -77,6 +79,7 @@ struct qcom_icc_desc { size_t num_clocks; bool is_bimc_node; const struct regmap_config *regmap_cfg; + unsigned int qos_offset; }; #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \