From patchwork Thu Dec 2 14:17:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 519843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AD30C43217 for ; Thu, 2 Dec 2021 14:18:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358520AbhLBOVl (ORCPT ); Thu, 2 Dec 2021 09:21:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358519AbhLBOV0 (ORCPT ); Thu, 2 Dec 2021 09:21:26 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76AF3C061784 for ; Thu, 2 Dec 2021 06:17:40 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id t26so71842609lfk.9 for ; Thu, 02 Dec 2021 06:17:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6/zIL8YkV/d4nljUzUQ3EO3Yb/Px31H+9eOQZUkZows=; b=yFe3VIuDiF2HeloldqKDVzEA4IYkyMvccBtnEUiRlVCBG+YvE05TW4M2c20kJbDm+s 8Sj18A/VD1MiiETWVrxjxSyxttfnozdB6IGJnds1W5Cn/O9WXv8rxwfriZbwimetLoDr yZwiO2W4P6C2pHGJP1gdhk4Hfg8OTMwDvgKC6sxee3s0T3L6aXxZG/2kgrFLWxK6UvWi PCrby6iTedngcnfU4RpLf1A+eyx2eXeGFOzmPBA3PCR4qnoZ9yLP07LorD5gVz1B3L04 NvqHvQNn5dto5rbxz3Hrb9sepTZxbNBA6Myik8umQV9ubPqKrCuiHGTdATBBwUWRP/Ps clug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6/zIL8YkV/d4nljUzUQ3EO3Yb/Px31H+9eOQZUkZows=; b=sFO7ZROO/N0pmBOG4huge0a2kvsbRBEUkHX9KCyaWFc4uuVjWTrYOq8hWXwjdAZCh0 j+XEWkr1LWYRY9nhvBMXviWUFqLSSkBBxrSujO7KsnPQ4GAXHmTuHoaQbMjWghDC+APN p8rXUrkonTC/t6iXyfGW6RN52U8+8XXbeXqG5di2mmB6wFSDK7GRAHZQ2bsT8QUGwPDJ 9oWB0RRsCqc+kLVWtD7EHeHL3K68YHQtY+LwWvNRfL/gaK8McezXMVyVSHK3KK+fjp6W tWsHIFFG1JYwZnDOJRcY5ysLDdcpM2AbBRZA+je8FvjzQbbyBYzKEXhkqYwJuJM6tD3p dDlA== X-Gm-Message-State: AOAM531tBdIexHD6q4OSJbgTOodayXR6HVlW8XXpJ9vwlWQgqMz/srik 9Z6bvvXtRnJ4vIrQcyA8qft7zQ== X-Google-Smtp-Source: ABdhPJzvu6wYr/1+YToSts0ncZnkplVB8E/G7vfYGcl3krUyERz6LIyDpd3Ry/OriVXwMgIMXaa6Rg== X-Received: by 2002:a05:6512:a95:: with SMTP id m21mr12552889lfu.574.1638454658759; Thu, 02 Dec 2021 06:17:38 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id m15sm362487lfg.165.2021.12.02.06.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 06:17:38 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Date: Thu, 2 Dec 2021 17:17:23 +0300 Message-Id: <20211202141726.1796793-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202141726.1796793-1-dmitry.baryshkov@linaro.org> References: <20211202141726.1796793-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree node for the first PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 3e1279f5114e..4e825291839a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -550,8 +550,12 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie0_lane>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "sleep_clk"; }; qupv3_id_0: geniqup@9c0000 { @@ -579,6 +583,40 @@ uart7: serial@99c000 { }; }; + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0 0x1c06e00 0 0x200>, /* tx */ + <0 0x1c07000 0 0x200>, /* rx */ + <0 0x1c06200 0 0x200>, /* pcs */ + <0 0x1c06600 0 0x200>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>;