From patchwork Fri Feb 4 14:46:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 540101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB6F3C41535 for ; Fri, 4 Feb 2022 14:46:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359411AbiBDOqv (ORCPT ); Fri, 4 Feb 2022 09:46:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345529AbiBDOqu (ORCPT ); Fri, 4 Feb 2022 09:46:50 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9235CC06173D for ; Fri, 4 Feb 2022 06:46:50 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id a28so13053295lfl.7 for ; Fri, 04 Feb 2022 06:46:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MEdow9qddiDDi5ISDFCGH7oeKbC5mGu6c1RrTKNWX/Y=; b=pxis1hg/jlw5nQXur7Gh7MiTW2H9lfVjjHk8A47b24zGh1f7tHppvK+MIUPUY4OY8n Dx05ufn+XyCnJZbceeUFgovtuRPY2k1gDGOhq2ioYQHyomz3Rnp0h9kd5hKVSvBQzfPP PL3F0T6kZ2h58IXCz9UMvkAG7VlLVxmBXuQ1KfiIpmjj3DOuDJd9/C+fGcN1xkhG86Ai TViDoAn5mTZwF7UdV7ijPvQfKfKC3cSfVYeIiEeWyoHH5RSU23DC7rjz/r1XPqN+1QxX 8WTg7EHgjBkAbSs/ydMNae2elZdfh8ERGf9tdm9zE+8RPl2czDFrvQk3Ls7ik/DBEYu0 r/5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MEdow9qddiDDi5ISDFCGH7oeKbC5mGu6c1RrTKNWX/Y=; b=skwU4kmHRQnt5mNAP89vP9Bv63iiaBl07+96HpmVDwFCGSSMa6jOPc7npKALy6aA55 ijsyWSmg3HZCSPqNYj56/+avwgW3nQ3AMBIUnMnm2v/5SKjiuG4WpuLMSO+SRcYpTH1w tQQgScvj1RgYUcRIByj0iFXXK/MK9L4bGVoRFSlDjKuGzxngohbom/RBp5wKSRQrrL2O A4HvFZ9uUfHf6u9SdSCCN//pXjmz60xrgyJge0COlB/MXki8/nS115+vRx3bqT7r9N2y c2I22m6Wq5hGLF2jcXSrjp0MmiaPtOKwBwhSf1T/Fgei3vmrWYqUXgP73VydHMrWEFEd 0ARw== X-Gm-Message-State: AOAM531TydW7NmMIOaG8psD38Qc8L6gH0HCCNn0RvgAXccCbq7iIHtYX Nj0GqzAnLwy2vYPoWZi+bMOqQg== X-Google-Smtp-Source: ABdhPJxuroIeSr4dcdPBz5jQ7IC0iZSdzhMqVc+7fGNygeMObTcH4hddM7moDZztQ897nFdhKsNRFw== X-Received: by 2002:ac2:5095:: with SMTP id f21mr2484888lfm.20.1643986008900; Fri, 04 Feb 2022 06:46:48 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y23sm348222lfb.2.2022.02.04.06.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 06:46:48 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Michael Turquette , Stephen Boyd Cc: Bjorn Helgaas , Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v2 02/11] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Date: Fri, 4 Feb 2022 17:46:36 +0300 Message-Id: <20220204144645.3016603-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> References: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use different set of clocks, so two compatible entries are required. Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.txt | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index da08f0f9de96..65a1fa74e4eb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -15,6 +15,8 @@ - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 - "qcom,pcie-ipq6018" for ipq6018 - reg: @@ -167,6 +169,20 @@ - "tbu" PCIe TBU clock - "ddrss_sf_tbu" PCIe SF TBU clock +- clock-names: + Usage: required for sm8450-pcie0 and sm8450-pcie1 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 + - "aggre1" Aggre NoC PCIe1 AXI clock + - resets: Usage: required Value type: @@ -244,7 +260,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sc8180x, sdm845 and sm8250 + Usage: required for sc8180x, sdm845, sm8250 and sm8450 Value type: Definition: Should contain the following entries - "pci" PCIe core reset