From patchwork Sat Apr 23 13:39:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A09D7C433FE for ; Sat, 23 Apr 2022 13:40:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235797AbiDWNnV (ORCPT ); Sat, 23 Apr 2022 09:43:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235831AbiDWNmn (ORCPT ); Sat, 23 Apr 2022 09:42:43 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35E001759FB for ; Sat, 23 Apr 2022 06:39:46 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id h27so18543701lfj.13 for ; Sat, 23 Apr 2022 06:39:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F1LrhyF1IFwxWcdCQmjBcgoDqXWko6Eulj2xB+qyGAU=; b=X8qNAwbtGVQ4LBIrvhBFsiBGbHLz0jpKeK7rGmXK524yZ3HX6XiG6AH/ISjQVGq71d ipT1wM7ADYYVlLct66ESdgbcqGRlH1MEdKz7fHd+sG9Kkvmfi5R2gQag8SJ9GEs/kq90 TjcXsCUUkCbhU1NTOr5vPieBt4Z1K1+2yOWxpGTGxF1ucOPgAxnVI1t8XYOvpAhrdZnq 5Xug3Tx7Lr+WzGO3Zi7/jLgmQXD0mfdDfquu4SCd5bd8uO4k7J1AcBBgDGvRdoTgvy7w ZTyLp1nwN0SSZRlr0Fc6nGaLRrFb+Z4ttpMP1XY9Ouss5dI4LRGrtxHmvMG4dMGrYh0b 1r5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F1LrhyF1IFwxWcdCQmjBcgoDqXWko6Eulj2xB+qyGAU=; b=6Y9ItesBeQCXuZn0oGhpYckHrf26tfaeNbFgpDpXYjPdEpD7MfH8eIEKbRkph63L0S C8E6vf7mhIhpG+H/rDTzIm9zXfZ2uXUH7rW+P97lwEJQArrt1vqi0UlrtoNakoMUKO6j NIwTW5um9sQi1zish++hcHzGVgpK5LNYL5igMzlGlswsaCLCxfwlcx+WLj7ZBo2rN1QQ n+8aUvpuoYjerZwSaxPRrOTEOIcr/JPXjKSQvewRnu5rjnkslIVOpohg3zDEdJCHHnBf 8snBx6CLr+2uB0qH+otJOWSTCzRAaDzhdG1UWqlKrx/odDMkHvPbUAnZxxTPtR3L6Zij ZyVg== X-Gm-Message-State: AOAM533iH1RMh6vu+qBvW3JXACIq6IH4VsFFytKS+VCI4JhEfCZk6Atb 6Z12TRQKLXMJPmcte4lfRrBBBg== X-Google-Smtp-Source: ABdhPJzutyKcEwX2MckmKMWVgTAc/ue8xrrn5S0lMn2zwB5NBhJd9t8stF1fob3BYWYuZEQxoSfy7g== X-Received: by 2002:a19:710a:0:b0:471:e7c8:a0db with SMTP id m10-20020a19710a000000b00471e7c8a0dbmr4480600lfc.512.1650721184466; Sat, 23 Apr 2022 06:39:44 -0700 (PDT) Received: from eriador.lumag.spb.ru ([94.25.228.223]) by smtp.gmail.com with ESMTPSA id c21-20020a2ea795000000b0024ee0f8ef92sm544535ljf.36.2022.04.23.06.39.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Apr 2022 06:39:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/5] PCI: dwc: Teach dwc core to parse additional MSI interrupts Date: Sat, 23 Apr 2022 16:39:36 +0300 Message-Id: <20220423133939.2123449-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> References: <20220423133939.2123449-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DWC driver parses a single "msi" interrupt which gets fired when the EP sends an MSI interrupt, however for some devices (Qualcomm) devies MSI vectors are handled in groups of 32 vectors. Add support for parsing "split" MSI interrupts. In addition to the "msi" interrupt, the code will lookup the "msi2", "msi3", etc. IRQs and use them for the MSI group interrupts. For backwards compatibility with existing DTS files, the code will not error out if any of these interrupts is missing. Instead it will limit itself to the amount of MSI group IRQs declared in the DT file. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 23 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 5d90009a0f73..ce7071095006 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -382,6 +382,29 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->msi_irq[0] = irq; } + if (pp->has_split_msi_irq) { + char irq_name[] = "msiXXX"; + int irq; + + for (ctrl = 1; ctrl < num_ctrls; ctrl++) { + if (pp->msi_irq[ctrl]) + continue; + + snprintf(irq_name, sizeof(irq_name), "msi%d", ctrl + 1); + irq = platform_get_irq_byname_optional(pdev, irq_name); + if (irq == -ENXIO) { + num_ctrls = ctrl; + pp->num_vectors = num_ctrls * MAX_MSI_IRQS_PER_CTRL; + dev_warn(dev, "Limiting amount of MSI irqs to %d\n", pp->num_vectors); + break; + } + if (irq < 0) + return irq; + + pp->msi_irq[ctrl] = irq; + } + } + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; ret = dw_pcie_allocate_domains(pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9c1a38b0a6b3..3aa840a5b19c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -179,6 +179,7 @@ struct dw_pcie_host_ops { struct pcie_port { bool has_msi_ctrl:1; + bool has_split_msi_irq:1; u64 cfg0_base; void __iomem *va_cfg0_base; u32 cfg0_size;