From patchwork Thu Apr 28 11:59:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 567225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55E8DC46467 for ; Thu, 28 Apr 2022 11:59:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345897AbiD1MC6 (ORCPT ); Thu, 28 Apr 2022 08:02:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345913AbiD1MC5 (ORCPT ); Thu, 28 Apr 2022 08:02:57 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 803DFABF4A for ; Thu, 28 Apr 2022 04:59:42 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id p12so8193517lfs.5 for ; Thu, 28 Apr 2022 04:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O2BucdX25yi/XV546unnoqK2cR6cu2U6EdyP9q7yCcs=; b=CRqlVrJ6RAiab3/cGrXcJ/cMByNz8OipWbfJqnKsd1vQd5a2/tOYg+bAEPtRFpqh87 pgv7TDirghwGG5qSiUSyFtk3ETVTEK8Rcmi8H8kpwFdyVuAtkFKKU2CKFmODhxIPLiTB S8o8zAoflUxnq6njeV1L/x2qJVVUioIg/xPqbEK1sa46cHw1vgzTQhN9jzXYnJi8BKZk r0DfIMviIrH9E7Ktl7DjiqzcLnJ+CW+du21Z31tBvD0WDBagut1mcAT+D7BT8AaVFGw4 EsEPHpTLBhUDOY0ZQHOZMJO5gsuJSVFyaMAausgYyqG01eUg/f3FMWS/Ab/27mARqyqw brYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O2BucdX25yi/XV546unnoqK2cR6cu2U6EdyP9q7yCcs=; b=41jB0iEqDCSV46PtZOZ63B3H36utcuyKT+IK6JCbJ42s7gCrXU+yH0+Vi2o4K1NIBC e9oQWHOmx1LVYWitqwmmAjv7R2P8bwgOWNL9XOQ2jbxOwGmu8g7qBfdi6E8jYbbZlmTX 0gPIG4+8q61vxQlkKSazrOI60OisGEYJ3D3AvJXtd1C4X+LcXXSssF2UWGVXtRrslayy 3KR+g0bVHbW87HKUUcAI1qOTfvAhorZ8nvuEyZ/OfAyHflz1ghTZuZc9excJZAmzku12 aOI5SECCEE7MbcJHXwRlrwluw6T6IU/ZbBHxbYz2WMLWNzh6TzHVKToYX9mK9PyEyxHp WsYQ== X-Gm-Message-State: AOAM530rp8K1Ior9bSP8te8ZwvHjTi/ZpEbVHR3Ev0HZ5PXoNYgW73gu 8RoQ02JKCNeFt+5/oPPD41emEg== X-Google-Smtp-Source: ABdhPJzf77VSRnnNz4wLdcNGgBTDPEj7essUksXDkLlyFzyEOHvMCMBT9aBIjk1jbyuu1jiboM/GuA== X-Received: by 2002:a05:6512:38a7:b0:471:ffe1:d7f1 with SMTP id o7-20020a05651238a700b00471ffe1d7f1mr16654895lft.216.1651147180434; Thu, 28 Apr 2022 04:59:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id f1-20020a2e1f01000000b0024602522b5dsm2069137ljf.120.2022.04.28.04.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 04:59:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 6/7] dt-bindings: pci/qcom,pcie: support additional MSI interrupts Date: Thu, 28 Apr 2022 14:59:33 +0300 Message-Id: <20220428115934.3414641-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220428115934.3414641-1-dmitry.baryshkov@linaro.org> References: <20220428115934.3414641-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 51 ++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..a8f99bca389e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,20 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: + minItems: 1 items: - const: msi + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: msi8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +632,46 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + minItems: 1 + maxItems: 1 + interrupt-names: + minItems: 1 + maxItems: 1 + - properties: + interrupts: + minItems: 8 + maxItems: 8 + interrupt-names: + minItems: 8 + maxItems: 8 + else: + properties: + interrupts: + minItems: 1 + maxItems: 1 + interrupt-names: + minItems: 1 + maxItems: 1 + unevaluatedProperties: false examples: