From patchwork Fri May 6 15:21:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 570227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CAECC43219 for ; Fri, 6 May 2022 15:21:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442797AbiEFPY5 (ORCPT ); Fri, 6 May 2022 11:24:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442779AbiEFPY5 (ORCPT ); Fri, 6 May 2022 11:24:57 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8874C6D19D for ; Fri, 6 May 2022 08:21:13 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id x17so13135301lfa.10 for ; Fri, 06 May 2022 08:21:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/QSONSEpjxrPZtFb9gmtNnByfU6eZhR98/Jc/QyZERA=; b=HWClHrabwkjxcA2CtSeU23o6GO2OMPDOjI2fw4har7wqRa2qhzfxFDlz0BCeoejIfO IDFEgmhezRdtbuAlKVd94wD37B04PS8/adyQMuqNipoAZO0/KnUfYk6hGlPRmVbXpVur nkH71JkDJfgjAvpIdtVYGZHMBs1govfvXhzH3F1jByooJWDS0H70fWlNdVT/lq8RRkFB GDxckoEPsZumrqGeKrhAePDInhv2/F1ZaM4L0wO+zmq0lMcGp/8S1uz12kwHgT3EWnIR 3mWi90gZbBMCVglu/5+FYQiRULw7HR34DZZ7UZHTu2vkf4rS5wfEVAJtI9tgPocbrG3L fZeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/QSONSEpjxrPZtFb9gmtNnByfU6eZhR98/Jc/QyZERA=; b=eeySJCWlddW5U+UFEswsKAskqwQQ5S9JJ/ryB+WtUmfLsIxNk31H7eoNPOQ6KvQkZj VZR8OyqI9kIrSzpUrGYAqnvc1d0lKUouj8z6E6GgvmJQR68QDGRIQ1m9iCnuTMBMmD0h FF1/hVCTzaa/4/McOiUuCSHxThSIHF8CndIRMjrfBfjudNMfWqHOTOBp5jBg9BPtM4Oq 24NUOqAmhKGbPpupstxUEhGu34yiuBENHLxC5M73qBo9vSvBfla6or75JKy6ombhurp8 m55d0n9AU7o3StuPmP1BzAk/aDBZrjD/Blv9gqPR7BcY5PzTisextRw0cdgtg6V0FTT7 KBnQ== X-Gm-Message-State: AOAM533VD09wcKWi0mfHaHEq8Ad60G2N8CMElY8NZtLN4mrtT8sx50NV xkm9OVxxjJne30y878e37MGYKg== X-Google-Smtp-Source: ABdhPJysUAIrL7QY6s4XuAbn/XZxOwZnTPUA14uicd/0xjxsBDKC0P+IVky1n8F0aFR5uMU0YFXKtg== X-Received: by 2002:a05:6512:3f01:b0:46b:a5ba:3b89 with SMTP id y1-20020a0565123f0100b0046ba5ba3b89mr2801120lfa.28.1651850471526; Fri, 06 May 2022 08:21:11 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id k16-20020a05651239d000b0047255d211e6sm716757lfu.277.2022.05.06.08.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 08:21:11 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v6 3/8] dt-bindings: PCI: qcom: Specify reg-names explicitly Date: Fri, 6 May 2022 18:21:02 +0300 Message-Id: <20220506152107.1527552-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220506152107.1527552-1-dmitry.baryshkov@linaro.org> References: <20220506152107.1527552-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Instead of specifying the enum of possible reg-names, specify them explicitly. This allows us to specify which chipsets need the "atu" regions, which do not. Also it clearly describes which platforms enumerate PCIe cores using the dbi region and which use parf region for that. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie.yaml | 91 +++++++++++++++++-- 1 file changed, 84 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index ce4f53cdaba0..e91ae436cafe 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -40,13 +40,6 @@ properties: reg-names: minItems: 4 maxItems: 5 - items: - enum: - - parf # Qualcomm specific registers - - dbi # DesignWare PCIe registers - - elbi # External local bus interface registers - - config # PCIe configuration space - - atu # ATU address space (optional) interrupts: maxItems: 1 @@ -117,6 +110,90 @@ required: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064v2 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: parf # Qualcomm specific registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq6018 + then: + properties: + reg: + minItems: 5 + maxItems: 5 + reg-names: + items: + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: parf # Qualcomm specific registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8084 + - qcom,pcie-msm8996 + - qcom,pcie-sdm845 + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8180x + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + properties: + reg: + minItems: 5 + maxItems: 5 + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - if: properties: compatible: