From patchwork Sun Jun 26 01:39:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Joseph S. Barrera III" X-Patchwork-Id: 585139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3072C433EF for ; Sun, 26 Jun 2022 01:40:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233714AbiFZBkJ (ORCPT ); Sat, 25 Jun 2022 21:40:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233709AbiFZBkG (ORCPT ); Sat, 25 Jun 2022 21:40:06 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A063F13D2B for ; Sat, 25 Jun 2022 18:40:04 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id g7so1079622pjj.2 for ; Sat, 25 Jun 2022 18:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mr7cpuqmRn6xpaNrj0168JJ9U51NmQAWQUP19BgumiU=; b=OR9A4AOHO6N9yAKE6mxPb7uJN62hb1QEBBRxVVY9/+aqPFjRCPHOti+KyEbYeR1ZRk DRkzki6dwewmbc1eK0vh9+1u6HICxBsoHEh9Y83GjcTaP0DCftvgSh9srHdnOwWtX+6S SDMwidxhxjyvqBMaxTeENS3D8miJtWGXRi0P4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mr7cpuqmRn6xpaNrj0168JJ9U51NmQAWQUP19BgumiU=; b=Mvo3OD+nFPuxIBkN11cq9mVvy+CtVtG9v3442Pr+RXGvWmy6FZS9JbOH/HDAD145HV zNSIUc+SQ0fPKpXhUYaCwKPAoFBlHhee8gngI6mixAR4yYg0cr8O+nBrOpdc52oKEn7m C090THar4/PP62ficFZ5xSBTGXuy74tPIk6BcIvkMQ8VXGylA4HQ+rNk4stMsI2ewJt/ Q3zg+ed1wBwP49Py7ApsAUpe865PChWSuCw5+NMgfk35oDCOclKTPKVutRhhOXOxtwsi 2Ihjrz+31SE1wQ0Z9k2opz8gZTfpOKJTIy2kWQGAnD2c6R7JUprXpfzBtGAVemPt9h8j 6zHw== X-Gm-Message-State: AJIora8vQHhBhhiI6jR+AwbuxIhx44cvM78ae6BigvMkCaKfw+wSeiXI 2YvzFYUcnEepWQOuL3mwwSt+dQ== X-Google-Smtp-Source: AGRyM1sKgDUgIK13oUZnEajGeYzcWT4DBxf2I7jR6SyVQ4aFzsrLNcDICU8VSzLod0L7C/JFeknVMw== X-Received: by 2002:a17:90a:e4c6:b0:1ed:4ffb:11f8 with SMTP id e6-20020a17090ae4c600b001ed4ffb11f8mr2981465pju.150.1656207603803; Sat, 25 Jun 2022 18:40:03 -0700 (PDT) Received: from joebar-glaptop.attlocal.net ([107.126.90.40]) by smtp.gmail.com with ESMTPSA id m13-20020a170902e40d00b00167838b82e0sm4283200ple.205.2022.06.25.18.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jun 2022 18:40:03 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Alexandru M Stan , Douglas Anderson , Stephen Boyd , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v14 3/5] arm64: dts: qcom: sc7180: Add mrbland dts files Date: Sat, 25 Jun 2022 18:39:04 -0700 Message-Id: <20220625183538.v14.3.I71176ebf7e5aebddb211f00e805b32c08376d1be@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220626013906.885523-1-joebar@chromium.org> References: <20220626013906.885523-1-joebar@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Mrbland is a trogdor-based board. These dts files are copies from the downstream Chrome OS 5.4 kernel, but with downstream bits removed. Signed-off-by: Joseph S. Barrera III Reviewed-by: Douglas Anderson --- (no changes since v7) Changes in v7: - Restore mrbland patch. - Only include sc7180.dtsi in sc7180-trogdor.dtsi (19794489fa24). - Simplify spi0/spi6 labeling (d277cab7afc7). - Simplify trackpad enabling (51d30402be75). Changes in v6: - Remove mrbland patch. Changes in v5: - Replace _ in node name with - - Order nodes by name. - Add comment that compatible will be filled in per-board. Changes in v4: - Add missing version history Changes in v2: - Add word wrapping to patch description. - Remove "Author" from patch description. - Fix whitespace around "en_pp3300_dx_edp". arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcom/sc7180-trogdor-mrbland-rev0-auo.dts | 22 ++ .../qcom/sc7180-trogdor-mrbland-rev0-boe.dts | 22 ++ .../dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi | 53 +++ .../qcom/sc7180-trogdor-mrbland-rev1-auo.dts | 22 ++ .../qcom/sc7180-trogdor-mrbland-rev1-boe.dts | 24 ++ .../boot/dts/qcom/sc7180-trogdor-mrbland.dtsi | 344 ++++++++++++++++++ 7 files changed, 491 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7268086f66e8..5cfd6316768c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -75,6 +75,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts new file mode 100644 index 000000000000..2767817fb053 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 => 0 + * - bits 7..4: Panel ID: 0x0 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model = "Google Mrbland rev0 AUO panel board"; + compatible = "google,mrbland-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts new file mode 100644 index 000000000000..711485574a03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 => 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model = "Google Mrbland rev0 BOE panel board"; + compatible = "google,mrbland-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi new file mode 100644 index 000000000000..7bc8402c018e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +&avdd_lcd { + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ +&avdd_lcd_en { + pinmux { + pins = "gpio80"; + }; + + pinconf { + pins = "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins = "gpio81"; + }; + + pinconf { + pins = "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins = "gpio76"; + }; + + pinconf { + pins = "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts new file mode 100644 index 000000000000..275313ef7554 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 => 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model = "Google Mrbland rev1+ AUO panel board"; + compatible = "google,mrbland-sku1536", "qcom,sc7180"; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts new file mode 100644 index 000000000000..87c6b6c30b5e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x300 => 768 + * - bits 11..8: Panel ID: 0x3 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model = "Google Mrbland (rev1 - 2) BOE panel board"; + /* Uses ID 768 on rev1 and 1024 on rev2+ */ + compatible = "google,mrbland-sku1024", "google,mrbland-sku768", + "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi new file mode 100644 index 000000000000..33d1d8a29038 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + avdd_lcd: avdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible = "regulator-fixed"; + regulator-name = "avee_lcd"; + + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avee_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + v1p8_mipi: v1p8-mipi { + compatible = "regulator-fixed"; + regulator-name = "v1p8_mipi"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_1800_en>; + + vin-supply = <&pp3300_a>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&dsi0 { + + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_reset_1800>; + avdd-supply = <&avdd_lcd>; + avee-supply = <&avee_lcd>; + pp1800-supply = <&v1p8_mipi>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5d { + compatible = "goodix,gt7375p"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_MRBLAND"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio85"; + }; + + pinconf { + pins = "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; +};