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[93.42.70.190]) by smtp.googlemail.com with ESMTPSA id t27-20020a17090616db00b0071cbc7487e1sm18025172ejd.69.2022.07.06.18.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 18:30:47 -0700 (PDT) From: Christian Marangi To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Ohad Ben-Cohen , Baolin Wang , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Cc: Christian Marangi Subject: [PATCH 1/3] hwspinlock: qcom: Add support for mmio usage to sfpb-mutex Date: Thu, 7 Jul 2022 03:30:14 +0200 Message-Id: <20220707013017.26654-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Allow sfpb-mutex to use mmio in addition to syscon. Signed-off-by: Christian Marangi Reviewed-by: Bjorn Andersson Reviewed-by: Baolin Wang --- drivers/hwspinlock/qcom_hwspinlock.c | 32 ++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c index 364710966665..23c913095bd0 100644 --- a/drivers/hwspinlock/qcom_hwspinlock.c +++ b/drivers/hwspinlock/qcom_hwspinlock.c @@ -19,6 +19,11 @@ #define QCOM_MUTEX_APPS_PROC_ID 1 #define QCOM_MUTEX_NUM_LOCKS 32 +struct qcom_hwspinlock_of_data { + u32 offset; + u32 stride; +}; + static int qcom_hwspinlock_trylock(struct hwspinlock *lock) { struct regmap_field *field = lock->priv; @@ -63,9 +68,20 @@ static const struct hwspinlock_ops qcom_hwspinlock_ops = { .unlock = qcom_hwspinlock_unlock, }; +static const struct qcom_hwspinlock_of_data of_sfpb_mutex = { + .offset = 0x4, + .stride = 0x4, +}; + +/* All modern platform has offset 0 and stride of 4k */ +static const struct qcom_hwspinlock_of_data of_tcsr_mutex = { + .offset = 0, + .stride = 0x1000, +}; + static const struct of_device_id qcom_hwspinlock_of_match[] = { - { .compatible = "qcom,sfpb-mutex" }, - { .compatible = "qcom,tcsr-mutex" }, + { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, + { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, { } }; MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); @@ -101,7 +117,7 @@ static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev, return regmap; } -static const struct regmap_config tcsr_mutex_config = { +static const struct regmap_config qcom_hwspinlock_mmio_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -112,18 +128,20 @@ static const struct regmap_config tcsr_mutex_config = { static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev, u32 *offset, u32 *stride) { + const struct qcom_hwspinlock_of_data *data; struct device *dev = &pdev->dev; void __iomem *base; - /* All modern platform has offset 0 and stride of 4k */ - *offset = 0; - *stride = 0x1000; + data = of_device_get_match_data(dev); + + *offset = data->offset; + *stride = data->stride; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return ERR_CAST(base); - return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config); + return devm_regmap_init_mmio(dev, base, &qcom_hwspinlock_mmio_config); } static int qcom_hwspinlock_probe(struct platform_device *pdev)