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[78.26.46.173]) by smtp.gmail.com with ESMTPSA id l12-20020a2ea80c000000b0025e0396786dsm98192ljq.93.2022.07.28.04.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jul 2022 04:38:03 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rajendra Nayak , Sibi Sankar Subject: [PATCH v2 08/11] soc: qcom: icc-bwmon: add per-variant quirks Date: Thu, 28 Jul 2022 13:37:45 +0200 Message-Id: <20220728113748.170548-9-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220728113748.170548-1-krzysztof.kozlowski@linaro.org> References: <20220728113748.170548-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org BWMON v5 lacks global interrupt registers. Other BWMON versions differ as well, so add quirks for easier customization of code flow. Cc: Rajendra Nayak Cc: Sibi Sankar Signed-off-by: Krzysztof Kozlowski --- drivers/soc/qcom/icc-bwmon.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index 058c35d8dbbe..2e4a0fdfbf54 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -100,6 +100,9 @@ #define BWMON_V4_ZONE_MAX(zone) (0x2e0 + 4 * (zone)) +/* Quirks for specific BWMON types */ +#define BWMON_HAS_GLOBAL_IRQ BIT(0) + enum bwmon_fields { F_GLOBAL_IRQ_CLEAR, F_GLOBAL_IRQ_ENABLE, @@ -136,6 +139,7 @@ struct icc_bwmon_data { unsigned int default_lowbw_kbps; u8 zone1_thres_count; u8 zone3_thres_count; + unsigned int quirks; const struct regmap_config *regmap_cfg; const struct reg_field *regmap_fields; @@ -270,14 +274,16 @@ static void bwmon_clear_irq(struct icc_bwmon *bwmon) * interrupt is cleared. */ regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], BWMON_IRQ_ENABLE_MASK); - regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR], - BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); + if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) + regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR], + BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); } static void bwmon_disable(struct icc_bwmon *bwmon) { /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */ - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0); + if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) + regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0); regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0); /* @@ -290,8 +296,9 @@ static void bwmon_disable(struct icc_bwmon *bwmon) static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) { /* Enable interrupts */ - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], - BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); + if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) + regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], + BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable); /* Enable bwmon */ @@ -543,6 +550,7 @@ static const struct icc_bwmon_data msm8998_bwmon_data = { .default_lowbw_kbps = 0, .zone1_thres_count = 16, .zone3_thres_count = 1, + .quirks = BWMON_HAS_GLOBAL_IRQ, .regmap_fields = msm8998_bwmon_reg_fields, .regmap_cfg = &msm8998_bwmon_regmap_cfg, };