From patchwork Wed Aug 17 14:57:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 598171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B512BC3F6B0 for ; Thu, 18 Aug 2022 04:17:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243156AbiHRERf (ORCPT ); Thu, 18 Aug 2022 00:17:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243072AbiHRERd (ORCPT ); Thu, 18 Aug 2022 00:17:33 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00AA798A53; Wed, 17 Aug 2022 21:17:29 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27I3KMjL029516; Thu, 18 Aug 2022 04:17:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=3h1aiXrphk5T2rqN3UBCgmzr+FGo6Il6A5/GglCrd1c=; b=fHEuCiWEGlgh15fqeTQp3Rw/MvaHK1fTO1t4uj5kQRSewaj5HCdxiGZ8OUWsQBipx8wF oPlMkSeaUr+1P4URn/yGMTYtmMcX5ShneHOyX9UteOFnSe3ubwap5YPoDHVcIH2cVMML VcE/zw3LCxw6/dhMc52/vKBzgHaObL7QwtBK9E6Ks5CHLKx5oxiRzogVeFy5e666pgob vHTwjdstI7LcVZh/QultH8QuAtPXXXA8Y/3tnTrjjh0CvS1akfH6YMMIrJFW6qbzr3Er 5YK41ER7+KUCwt5A8gZvMqrOWBEMTqU0XL3Wjo0qDw2ktkOsLeLh+QQc2CdegJhBmlNE pQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j1d8009f3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 04:17:22 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27I4HJ0r012608 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 04:17:21 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 17 Aug 2022 07:58:41 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH v2 5/5] arm64: dts: qcom: sc7280: Add Reset support for gpu Date: Wed, 17 Aug 2022 20:27:54 +0530 Message-ID: <20220817202609.v2.5.I6a1fca5d53c886c05ea3e24cd4282d31c9c0cd0b@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660748274-39239-1-git-send-email-quic_akhilpo@quicinc.com> References: <1660748274-39239-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AwGgKFkFnmSILa68FFx3WQfj8w4OP4u0 X-Proofpoint-ORIG-GUID: AwGgKFkFnmSILa68FFx3WQfj8w4OP4u0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_02,2022-08-16_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180014 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Reset using GPUCC driver for GPU. This helps to ensure that GPU state is reset by making sure that CX head switch is collapsed. Signed-off-by: Akhil P Oommen --- (no changes since v1) arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e66fc67..f5257d6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2243,6 +2243,9 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + resets = <&gpucc GPU_CX_COLLAPSE>; + reset-names = "cx_collapse"; + gpu_opp_table: opp-table { compatible = "operating-points-v2";