From patchwork Fri Sep 9 09:14:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 604274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55575C6FA86 for ; Fri, 9 Sep 2022 09:14:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231960AbiIIJOq (ORCPT ); Fri, 9 Sep 2022 05:14:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232090AbiIIJOm (ORCPT ); Fri, 9 Sep 2022 05:14:42 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EFF29583 for ; Fri, 9 Sep 2022 02:14:40 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id l12so1067622ljg.9 for ; Fri, 09 Sep 2022 02:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=QVU+UE1EBysRzdp8C3u3a6aWiuWRGj3Z9ISz0CxJ14s=; b=OKHr8RdKD9EhTKcN1thF3eGKdstebYgTaLc9RFPp00s3JLJ0XOsqGqO07q+o8P+TSA A24Nt5mnCdJtWRGlDgS0RWQmqwdBrIM3M2Hs5jGeXRUb2NYled2Jfu0WS/kIGJCrFv3p fuBLZ/Y4CdZoyUAvoACqFI/R+JZVlFcWXwh5SkQcFpxKubMG1deIutcEzfYGJu1mPInF qQ1di+XnwyFsLPV5REL88th6MprTcHbFoJFfZ1HrCuD3dFzqU1YUgT6bEuj8zQ88J+rz YAmX6Mc6XnaVk6yyHNAPIDL7bsRbs5qfTOIrErnPMxcdI1y4+m+vnvMeqgJ9VCWGrUjM Bmnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=QVU+UE1EBysRzdp8C3u3a6aWiuWRGj3Z9ISz0CxJ14s=; b=Lvnt55SJZc3eR80QSibqIypEUTsbMMUT5kiLz7sJo/GpwKkhi3aHllTiYVIelG6XGt ep8vSvEDWjrqo/g2/J5brmY6q0YjI3JM8g168RqAUoqjRQ5wmby+LLjQNdIHxrtM/PyO DPNEFrilRBjdqTniXhoKnrKd6FYwnCEtsY3AEoVBe37xusKOK/4qst79/mS/CpZgTzFI icswIPjRAE9njD+n4wnwSdff+Ap0CV3PrTzFspI0e4ZO2GZclgAL7ktSBbUD4oDXmAan Oorg0qK+FYHR5Y4d5fX6e8+j3B2F15qgPrfEe1zQPkcJUv7FmoPsJvzB6FSx6bRO9oSd U6wQ== X-Gm-Message-State: ACgBeo1T7/tvqKmljWqsrHke4E+CBiLl6PxPTo+cGcbGgJw0Dw0FTqJa Z9ukDLfaVwATBMulw/9fVmN69A== X-Google-Smtp-Source: AA6agR6MkCfQZE4VRnkdK44y+9KMn8oo1xI27A0WO+/R0RGWxiXBd8yfCRQNyBwoTSaD9ZF0QpBc/Q== X-Received: by 2002:a2e:9b89:0:b0:26a:a004:ac3 with SMTP id z9-20020a2e9b89000000b0026aa0040ac3mr3434130lji.104.1662714878740; Fri, 09 Sep 2022 02:14:38 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id z26-20020a2e4c1a000000b0026acbb6ed1asm201615lja.66.2022.09.09.02.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 02:14:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 4/9] phy: qcom-qmp-pcie: split PHY programming to separate functions Date: Fri, 9 Sep 2022 12:14:28 +0300 Message-Id: <20220909091433.3715981-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220909091433.3715981-1-dmitry.baryshkov@linaro.org> References: <20220909091433.3715981-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split the code using PHY programming tables into separate functions, which take a single struct qmp_phy_cfg_tables instance. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 92 +++++++++++++----------- 1 file changed, 49 insertions(+), 43 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index ca8dffaf1081..5250c3f06c89 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1949,15 +1949,54 @@ static void qcom_qmp_phy_pcie_configure(void __iomem *base, qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff); } -static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) +static void qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->main.serdes_tbl, cfg->main.serdes_tbl_num); - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->secondary.serdes_tbl, cfg->secondary.serdes_tbl_num); + if (!tables) + return; - return 0; + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, tables->serdes_tbl, tables->serdes_tbl_num); +} + +static void qcom_qmp_phy_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + + if (!tables) + return; + + qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, + tables->tx_tbl, tables->tx_tbl_num, 1); + + if (cfg->is_dual_lane_phy) + qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, + tables->tx_tbl, tables->tx_tbl_num, 2); + + qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, + tables->rx_tbl, tables->rx_tbl_num, 1); + if (cfg->is_dual_lane_phy) + qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, + tables->rx_tbl, tables->rx_tbl_num, 2); +} + +static void qcom_qmp_phy_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; + void __iomem *pcs_misc = qphy->pcs_misc; + + if (!tables) + return; + + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, + tables->pcs_tbl, tables->pcs_tbl_num); + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, + tables->pcs_misc_tbl, + tables->pcs_misc_tbl_num); } static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) @@ -2041,15 +2080,13 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *tx = qphy->tx; - void __iomem *rx = qphy->rx; void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; void __iomem *status; unsigned int mask, val, ready; int ret; - qcom_qmp_phy_pcie_serdes_init(qphy); + qcom_qmp_phy_pcie_serdes_init(qphy, &cfg->main); + qcom_qmp_phy_pcie_serdes_init(qphy, &cfg->secondary); ret = clk_prepare_enable(qphy->pipe_clk); if (ret) { @@ -2058,42 +2095,11 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) } /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, - cfg->main.tx_tbl, cfg->main.tx_tbl_num, 1); - qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, - cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 1); + qcom_qmp_phy_pcie_lanes_init(qphy, &cfg->main); + qcom_qmp_phy_pcie_lanes_init(qphy, &cfg->secondary); - /* Configuration for other LANE for USB-DP combo PHY */ - if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, - cfg->main.tx_tbl, cfg->main.tx_tbl_num, 2); - qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, - cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 2); - } - - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, - cfg->main.rx_tbl, cfg->main.rx_tbl_num, 1); - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, - cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 1); - - if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, - cfg->main.rx_tbl, cfg->main.rx_tbl_num, 2); - qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, - cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 2); - } - - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, - cfg->main.pcs_tbl, cfg->main.pcs_tbl_num); - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, - cfg->secondary.pcs_tbl, cfg->secondary.pcs_tbl_num); - - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, - cfg->main.pcs_misc_tbl, - cfg->main.pcs_misc_tbl_num); - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, - cfg->secondary.pcs_misc_tbl, - cfg->secondary.pcs_misc_tbl_num); + qcom_qmp_phy_pcie_pcs_init(qphy, &cfg->main); + qcom_qmp_phy_pcie_pcs_init(qphy, &cfg->secondary); /* * Pull out PHY from POWER DOWN state.