From patchwork Wed Sep 14 16:25:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 606284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2A00C6FA8D for ; Wed, 14 Sep 2022 16:26:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229615AbiINQ0p (ORCPT ); Wed, 14 Sep 2022 12:26:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229653AbiINQ0k (ORCPT ); Wed, 14 Sep 2022 12:26:40 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A2917D7BA; Wed, 14 Sep 2022 09:26:40 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AA9F3619F6; Wed, 14 Sep 2022 16:26:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BEB6C41675; Wed, 14 Sep 2022 16:26:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663172799; bh=cRAr0sH1CJQ/Ys6irbpZpXb6p7rK6u+Isb1FskBrSNU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XgIXWDdMTAijdudLA+17fEoOUh8A/armGZuNzdd+EBLdmG+5wPTL0e2cyz2qddx7a HCPt4LFmolAG5xD+PSfJir8pjyiegxPXKdliAamypj860ko0bo7fb2ByKfuraQWMWZ bUsN91fgordRz3WTAOch70RYv+AbD3AlMzZ8WCJmDhiMkljbKu7LTTE2hk7eEz6lu1 64kEDinzzEdHrPhB31rqheYHWOVnFQMaK0WZpYT9xYjB4NvXOpGhoS/b+TuXx3ueNM uDbEyrH5a8FGODRck+cFoVKF/78gp/o9dk+Pv7wpVo5jO5EPah7jOt70DbgNKnRc4Q lLqcBo30WcoCg== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oYVDk-0001ex-85; Wed, 14 Sep 2022 18:26:40 +0200 From: Johan Hovold To: Vinod Koul Cc: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 10/11] phy: qcom-qmp-ufs: drop legacy DT workaround Date: Wed, 14 Sep 2022 18:25:44 +0200 Message-Id: <20220914162545.6289-11-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220914162545.6289-1-johan+linaro@kernel.org> References: <20220914162545.6289-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Commit 5e17b95d9893 ("phy: qcom-qmp: Utilize fully-specified DT registers") added a workaround for legacy devicetrees which did not specify register regions for the second lane of some dual-lane PHYs. At the time, the only two dual-lane PHYs supported by mainline were "qcom,sdm845-qmp-usb3-phy" and "qcom,sdm845-qmp-ufs-phy" and they had been added to the binding less than six months before the binding was fixed. Presumably no one is using four-year old SDM845 dtbs with mainline anymore so drop the workaround for malformed devicetrees. In the unlikely event that anyone complains, we can consider reverting. Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 27 ++++++------------------- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 1b1ac20cf290..7b335b50b4a1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -38,9 +38,6 @@ #define PHY_INIT_COMPLETE_TIMEOUT 10000 -/* Define the assumed distance between lanes for underspecified device trees. */ -#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 - struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -1137,28 +1134,16 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, if (IS_ERR(qphy->pcs)) return PTR_ERR(qphy->pcs); - /* - * If this is a dual-lane PHY, then there should be registers for the - * second lane. Some old device trees did not specify this, so fall - * back to old legacy behavior of assuming they can be reached at an - * offset from the first lane. - */ if (cfg->is_dual_lane_phy) { qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { - dev_warn(dev, - "Underspecified device tree, falling back to legacy register regions\n"); + if (IS_ERR(qphy->tx2)) + return PTR_ERR(qphy->tx2); - /* In the old version, pcs_misc is at index 3. */ - qphy->pcs_misc = qphy->tx2; - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; - - } else { - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); - } + qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qphy->rx2)) + return PTR_ERR(qphy->rx2); + qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } else { qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); }