From patchwork Wed Oct 5 09:07:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 612579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62C5AC4321E for ; Wed, 5 Oct 2022 09:07:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229770AbiJEJHy (ORCPT ); Wed, 5 Oct 2022 05:07:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229543AbiJEJHw (ORCPT ); Wed, 5 Oct 2022 05:07:52 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1765760F0; Wed, 5 Oct 2022 02:07:51 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29590MI5019005; Wed, 5 Oct 2022 09:07:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=yTjmXTJTL0m+AUUrj2ObPl+pUncLDzooc+5ieL1P0bs=; b=eOPbdjxvCfK4rNyLljVafL0lvorBiDY1LMTkEDitpxzlppdkGpRqsILZbvYs3Ad9lHTA e2Wz3PznGuX504I1v1Cf+PBYdBLRVtvQUmiofd1liH9N00FlPyd6hZ3mGB3NzMCm/MWX HqyHHZNq2n2NbvOT98T+RHOxd6kivjb0YsIgfgTffps7uHi8FfI9W18DoRga/Af0birS G31kjMQgJ2ek9BnapQTlc2c9SDsDk0eOLe5LhEXeAq6KtUTBk8xUPv0VjPIv0dmdhHF+ mu7kSMh69/0sm1VEn4JckrEiYxXcPa7oHYyRS6aNQfaQphABdN86BERsGkPpN2gCOmZh /w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k0jtdjfpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:07:40 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29597djo000910 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:07:39 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:34 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , , Subject: [PATCH v7 2/6] clk: qcom: Allow custom reset ops Date: Wed, 5 Oct 2022 14:37:00 +0530 Message-ID: <20221005143618.v7.2.I75baff799a363bbb960376539e3a0f737377c3f1@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nDgqOmhTpEoIdgZnL772SocnNQj5_ihz X-Proofpoint-ORIG-GUID: nDgqOmhTpEoIdgZnL772SocnNQj5_ihz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Allow soc specific clk drivers to specify a custom reset operation. We will use this in an upcoming patch to allow gpucc driver to specify a differet reset operation for cx_gdsc. Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- (no changes since v3) Changes in v3: - Use pointer to const for "struct qcom_reset_ops" in qcom_reset_map (Krzysztof) Changes in v2: - Return error when a particular custom reset op is not implemented. (Dmitry) drivers/clk/qcom/reset.c | 27 ++++++++++++++++++++++++++- drivers/clk/qcom/reset.h | 8 ++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c index 2a16adb..10ef71b 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c @@ -13,7 +13,20 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id) { - struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev); + struct qcom_reset_controller *rst; + const struct qcom_reset_map *map; + + rst = to_qcom_reset_controller(rcdev); + map = &rst->reset_map[id]; + + if (map->ops && map->ops->reset) + return map->ops->reset(map->priv); + /* + * If custom ops is implemented but just not this callback, return + * error + */ + else if (map->ops) + return -EOPNOTSUPP; rcdev->ops->assert(rcdev, id); udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */ @@ -30,6 +43,12 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; + + if (map->ops && map->ops->assert) + return map->ops->assert(map->priv); + else if (map->ops) + return -EOPNOTSUPP; + mask = BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, mask); @@ -44,6 +63,12 @@ qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; + + if (map->ops && map->ops->deassert) + return map->ops->deassert(map->priv); + else if (map->ops) + return -EOPNOTSUPP; + mask = BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, 0); diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h index b8c1135..a4d767b 100644 --- a/drivers/clk/qcom/reset.h +++ b/drivers/clk/qcom/reset.h @@ -8,10 +8,18 @@ #include +struct qcom_reset_ops { + int (*reset)(void *priv); + int (*assert)(void *priv); + int (*deassert)(void *priv); +}; + struct qcom_reset_map { unsigned int reg; u8 bit; u8 udelay; + const struct qcom_reset_ops *ops; + void *priv; }; struct regmap;