From patchwork Wed Oct 12 08:12:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 614851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1CF0C433FE for ; Wed, 12 Oct 2022 08:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbiJLIQA (ORCPT ); Wed, 12 Oct 2022 04:16:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229868AbiJLIP5 (ORCPT ); Wed, 12 Oct 2022 04:15:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AD555E325; Wed, 12 Oct 2022 01:15:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B6B8F61472; Wed, 12 Oct 2022 08:15:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 186EAC433D7; Wed, 12 Oct 2022 08:15:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665562555; bh=HNlikP9dVSVRk63ElYvGEtZ7q8+SwsvKpLRsfypMh6k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EtEyJB1kYUoZH+An3WssbIKuJmVpPrS1mGFw/uxyo29A8IVm53+76abJq6lBhEn3+ OOLVTie7EOypZ3VAHgJ8CMZdMf83Z+s4vgen0w+k4x7+Hq0/0+nKwHoziv4V+z4xbI +Tx/AzR0hNysyAJi6Fl5aZzVCKMatVKYBM/kVdRYZBZeVGE2Yzsyfdnm1Zalz/R+hJ akwr8O0rLmTG53LeiRBaUs1vpPOg9J75vXGWN85MhXbsFYyAF7Q/UJaMkrBAWvnpN4 32wMuHMDS7QEd+t2jmihlf+J5UPVCunp9rec1+MJsV7/127CLsOWAPDyvIpZEy9W/m pRtB6DjLSFzkw== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oiWu2-0004oV-IL; Wed, 12 Oct 2022 10:15:46 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 05/14] phy: qcom-qmp-pcie-msm8996: drop unused in-layout configuration Date: Wed, 12 Oct 2022 10:12:32 +0200 Message-Id: <20221012081241.18273-6-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221012081241.18273-1-johan+linaro@kernel.org> References: <20221012081241.18273-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MSM8996 QMP PCIe PHY driver no longer uses the "in-layout" configuration macro to configure registers that are typically accessed using "regs_layout" arrays (e.g. QPHY_START_CTRL) so drop this unused feature. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 34 ++++--------------- 1 file changed, 6 insertions(+), 28 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 8b74948eb467..31ac405d3785 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -46,11 +46,6 @@ struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; - /* - * register part of layout ? - * if yes, then offset gives index in the reg-layout - */ - bool in_layout; /* * mask of lanes for which this register is written * for cases when second lane needs different values @@ -65,14 +60,6 @@ struct qmp_phy_init_tbl { .lane_mask = 0xff, \ } -#define QMP_PHY_INIT_CFG_L(o, v) \ - { \ - .offset = o, \ - .val = v, \ - .in_layout = true, \ - .lane_mask = 0xff, \ - } - #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ { \ .offset = o, \ @@ -346,7 +333,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { }; static void qmp_pcie_msm8996_configure_lane(void __iomem *base, - const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num, u8 lane_mask) @@ -361,19 +347,15 @@ static void qmp_pcie_msm8996_configure_lane(void __iomem *base, if (!(t->lane_mask & lane_mask)) continue; - if (t->in_layout) - writel(t->val, base + regs[t->offset]); - else - writel(t->val, base + t->offset); + writel(t->val, base + t->offset); } } static void qmp_pcie_msm8996_configure(void __iomem *base, - const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num) { - qmp_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); + qmp_pcie_msm8996_configure_lane(base, tbl, num, 0xff); } static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy) @@ -387,7 +369,7 @@ static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy) unsigned int mask, val; int ret; - qmp_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + qmp_pcie_msm8996_configure(serdes, serdes_tbl, serdes_tbl_num); qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], @@ -531,13 +513,9 @@ static int qmp_pcie_msm8996_power_on(struct phy *phy) } /* Tx, Rx, and PCS configurations */ - qmp_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl, - cfg->tx_tbl_num, 1); - - qmp_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl, - cfg->rx_tbl_num, 1); - - qmp_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_pcie_msm8996_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_pcie_msm8996_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); + qmp_pcie_msm8996_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); /* * Pull out PHY from POWER DOWN state.