From patchwork Tue Oct 25 18:06:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 618897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEACCFA3742 for ; Tue, 25 Oct 2022 18:06:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232569AbiJYSG4 (ORCPT ); Tue, 25 Oct 2022 14:06:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232553AbiJYSGy (ORCPT ); Tue, 25 Oct 2022 14:06:54 -0400 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [IPv6:2001:4b7a:2000:18::162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97FAA11F for ; Tue, 25 Oct 2022 11:06:52 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2a00:f41:181d:45ba:3479:f7c2:4c21:3ad3]) (using TLSv1.3 with cipher TLS_CHACHA20_POLY1305_SHA256 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA512) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id CFFB1200D7; Tue, 25 Oct 2022 20:06:49 +0200 (CEST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Iskren Chernev , Thierry Reding , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: qcom: Add initial device tree for SM6375 Date: Tue, 25 Oct 2022 20:06:32 +0200 Message-Id: <20221025180634.28956-3-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221025180634.28956-1-konrad.dybcio@somainline.org> References: <20221025180634.28956-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add an initial device tree for the SM6375 (SD695) SoC. Signed-off-by: Konrad Dybcio --- Changes since v1: - Remove the xo_board freq from SoC DTSI arch/arm64/boot/dts/qcom/sm6375.dtsi | 807 +++++++++++++++++++++++++++ 1 file changed, 807 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6375.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi new file mode 100644 index 000000000000..c40a01f5b467 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + local-timer-stop; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sm6375", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0 0x80000000 0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@80700000 { + reg = <0 0x80700000 0 0x100000>; + no-map; + }; + + reserved_xbl_uefi: memory@80880000 { + reg = <0 0x80880000 0 0x14000>; + no-map; + }; + + smem_mem: smem@80900000 { + reg = <0 0x80900000 0 0x200000>; + no-map; + }; + + fw_mem: memory@80b00000 { + reg = <0 0x80b00000 0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: memory@80c00000 { + reg = <0 0x80c00000 0 0x1e00000>; + no-map; + }; + + dfps_data_mem: memory@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + pil_wlan_mem: memory@86500000 { + reg = <0 0x86500000 0 0x200000>; + no-map; + }; + + pil_adsp_mem: memory@86700000 { + reg = <0 0x86700000 0 0x2000000>; + no-map; + }; + + pil_cdsp_mem: memory@88700000 { + reg = <0 0x88700000 0 0x1e00000>; + no-map; + }; + + pil_video_mem: memory@8a500000 { + reg = <0 0x8a500000 0 0x500000>; + no-map; + }; + + pil_ipa_fw_mem: memory@8aa00000 { + reg = <0 0x8aa00000 0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@8aa10000 { + reg = <0 0x8aa10000 0 0xa000>; + no-map; + }; + + pil_gpu_micro_code_mem: memory@8aa1a000 { + reg = <0 0x8aa1a000 0 0x2000>; + no-map; + }; + + pil_mpss_wlan_mem: memory@8b800000 { + reg = <0 0x8b800000 0 0x10000000>; + no-map; + }; + + removed_mem: memory@c0000000 { + reg = <0 0xc0000000 0 0x5100000>; + no-map; + }; + + debug_mem: memory@ffb00000 { + reg = <0 0xffb00000 0 0xc0000>; + no-map; + }; + + last_log_mem: memory@ffbc0000 { + reg = <0 0xffbc0000 0 0x80000>; + no-map; + }; + + cmdline_region: memory@ffd00000 { + reg = <0 0xffd00000 0 0x1000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6375"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6375-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + + smem: smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + ipcc: mailbox@208000 { + compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; + reg = <0 0x00208000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6375-tlmm"; + reg = <0 0x00500000 0 0x800000>; + interrupts = ; + gpio-ranges = <&tlmm 0 0 157>; + /* TODO: Hook up MPM as wakeup-parent when it's there */ + interrupt-controller; + gpio-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,sm6375-gcc"; + reg = <0 0x01400000 0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb_1_hsphy: phy@162b000 { + compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x0162b000 0 0x400>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + #phy-cells = <0>; + + status = "disabled"; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x01c40000 0 0x1100>, + <0 0x01e00000 0 0x2000000>, + <0 0x03e00000 0 0x100000>, + <0 0x03f00000 0 0xa0000>, + <0 0x01c0a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0 0x045f0000 0 0x7000>; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; + reg = <0 0x04ef8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + /* + * This property is there to allow USB2 to work, as + * USB3 is not implemented yet - (re)move it when + * proper support is in place. + */ + qcom,select-utmi-as-pipe-clk; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0 0x04e00000 0 0xcd00>; + interrupts = ; + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0xe0 0x0>; + + /* Yes, this impl *does* have an unfunny number of quirks.. */ + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; + reg = <0 0x0c600000 0 0x100000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, + <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, + <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ + <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + #redistributor-regions = <1>; + #interrupt-cells = <3>; + redistributor-stride = <0 0x20000>; + interrupt-controller; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0x0f420000 0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@f423000 { + reg = <0x0f243000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};