From patchwork Thu Nov 10 10:35:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 623937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF29C4332F for ; Thu, 10 Nov 2022 10:38:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230087AbiKJKiX (ORCPT ); Thu, 10 Nov 2022 05:38:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbiKJKiU (ORCPT ); Thu, 10 Nov 2022 05:38:20 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9CA66C70B; Thu, 10 Nov 2022 02:38:19 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 57BAE60FB2; Thu, 10 Nov 2022 10:38:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BCDEC43144; Thu, 10 Nov 2022 10:38:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668076698; bh=4cWs27Yj/yVYtIlwKTVgGaBMfe52K43D9R9vlrRWLzo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MHKF8CSUMhpCmTUnsyytzYgdeOR5BKOlZgRRe6+Q0HAYmuNoYYr/mMov4BxQts1wf KHs3iJvYo1lrAD0ekErCfBaNC8/wjRxnAWhxPAY6B4r+wHCvQroPQaWxvVh2l5lTrg Q6NDt47ZM2UqjbLkiYU0f3VKf5d6SgIUVNsdt/+fgMclW2JwgHFgpMg7ThAcgiMr9f /FHebGu8/ql4eKUDjK4axF8B6/nYRYVw/YEaxvNCp1DSE74D2t4j2LVtNx8cSjsYfv oE5ZtjwGcdG8+2p5x5I8VeEHTkZpNAoWzF08gBET6CjQJ1Nvq2G62SSzYSDLk0uU+M 1Gzi/2hFrLl/A== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ot4wR-0003LV-1s; Thu, 10 Nov 2022 11:37:51 +0100 From: Johan Hovold To: Bjorn Andersson Cc: Andy Gross , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 4/9] arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD Date: Thu, 10 Nov 2022 11:35:53 +0100 Message-Id: <20221110103558.12690-5-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221110103558.12690-1-johan+linaro@kernel.org> References: <20221110103558.12690-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the NVMe SSD connected to PCIe2. Signed-off-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 0801bd8c44fb..fd2bdfd1126b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -50,6 +50,20 @@ vreg_edp_bl: regulator-edp-bl { regulator-boot-on; }; + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VCC3_SSD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + }; + vreg_misc_3p3: regulator-misc-3p3 { compatible = "regulator-fixed"; @@ -178,6 +192,25 @@ vreg_l9d: ldo9 { }; }; +&pcie2a { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &pmc8280c_lpg { status = "okay"; }; @@ -393,6 +426,36 @@ reset-pins { }; }; + nvme_reg_en: nvme-reg-en-state { + pins = "gpio135"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie2a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup0_i2c4_default: qup0-i2c4-default-state { pins = "gpio171", "gpio172"; function = "qup4";