From patchwork Fri Nov 11 14:59:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 625762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48B44C43219 for ; Fri, 11 Nov 2022 15:00:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234842AbiKKO74 (ORCPT ); Fri, 11 Nov 2022 09:59:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234696AbiKKO7d (ORCPT ); Fri, 11 Nov 2022 09:59:33 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B34B8654C5; Fri, 11 Nov 2022 06:59:31 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 171966602A5B; Fri, 11 Nov 2022 14:59:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668178770; bh=v/SdConwcLDUdB+vnhsUHtZDsg7PCN+jxysiLSvSwfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YuAw4h1USZuYNtGIaP6keEe/eLKOeSIf/5tQleLSFTXcIT42TOAqp9qF+GDluirO4 sCWOD1UqLTGVjNYDYV7Q1Qp5Mk0gj2FKqAWqhssUdLm4rLmktjE7r5amdn7qTJAUoe 8/1M807zf/RQTpzuJ1hD/XnJUcdnATFONhHpa5NuP1Vbvrn/lJWcoWEw9pryXo+aCO PsP4MwitdKWT28YOvZW6YFTPrDkfwXCPHuknDNKEmX5CkSOyTtWRT4lG5HFYhYzI5d 53A/IdpRUNXN2e14DtX3IAI5LbusGdPKLIprYyzqRGNRvnCrqXIYLgX46jGtiIjx7J 3ZwBwtb3e2pZA== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robdclark@gmail.com, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH v2 3/8] iommu/arm-smmu: Add definition for ARM_SMMU_CB_FSRRESTORE Date: Fri, 11 Nov 2022 15:59:14 +0100 Message-Id: <20221111145919.221159-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111145919.221159-1-angelogioacchino.delregno@collabora.com> References: <20221111145919.221159-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation for adding a proper context bank reset sequence in qcom_iommu, add a definition for the implementation defined Fault Status Restore register (FSRRESTORE). Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 703fd5817ec1..5015138799c5 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -219,6 +219,7 @@ enum arm_smmu_cbar_type { ARM_SMMU_FSR_TF | \ ARM_SMMU_FSR_IGN) +#define ARM_SMMU_CB_FSRRESTORE 0x5c #define ARM_SMMU_CB_FAR 0x60 #define ARM_SMMU_CB_FSYNR0 0x68