From patchwork Wed Nov 30 10:29:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 630371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0521C433FE for ; Wed, 30 Nov 2022 10:30:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235984AbiK3KaQ (ORCPT ); Wed, 30 Nov 2022 05:30:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235647AbiK3K3w (ORCPT ); Wed, 30 Nov 2022 05:29:52 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29E1A3FB86 for ; Wed, 30 Nov 2022 02:29:51 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id m14so2391750wrh.7 for ; Wed, 30 Nov 2022 02:29:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fOlQTs4BeJdJIZ8+9JnI4IeWM1eTgBEDEciqtN1gR1w=; b=AyMCzPSakgnC/cgoqR6abpP721IhzXUCsUed19mkRJnH8EUO57j12Z1hAM+MC5eSnr 07nB4DnylCUEf3R3uHdN5ZvATcLDnlO8dnWP1eDZ5x6eNqzmwDEyctKAxAtGi2AEiaqY uNDvHs5v06naSp9WefF9ZoyMzEHZwMAVmbbjvj9mFli6BppMQmLZQrLiH+QR8Wkn9QVt C9kcHzJ7P0vnmY81ybgom+nMisJADE615S7yKFdhsS4v8ur1bZ3M6JekpEd8VimEuEzj RuKYHiOg2xnncWZZmnYkpA9eHhJ8tY24T3TAxB/wjNK1YSeNeRNuBVpffwpJboqpqT81 KO7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fOlQTs4BeJdJIZ8+9JnI4IeWM1eTgBEDEciqtN1gR1w=; b=ryP8CmwQt8IzOiDv27P/us/vKEQjCRgvD/9Q4+ENDQlLRznnBWgN06U908eZBLVQIq LLLKKFygKzLTbr5NejEkqVctNOQDXK8lnGELt766hiMn0e+UbVMxyn4xer2VOrekOx/2 BptkoklyPDhxVqEFThIoZLqSU0aLnNEggHsJv1G1CkW6XemBdWpHqpjFJ4QzbAk1EDx0 Xpk+2rXeb4e7cNE8b27Qgnuy7VB2g+HJBSktbLUAQ0LaF6a9mjEzeSDHCMz6q6myhG0b XmWn3xMxN4y2jwS9rURT2PtOzmELqiLP7Ohqc9KQH4Pk8Fqz+0zXeyHh0cfBnkSxTtYm 7RwQ== X-Gm-Message-State: ANoB5plYEWIyq1zQS85E7r4bDgYSMy7ZgiTlHFpq/8TkqZjbR/LskX5s 2d77UdMfbmjTQ/kp4jLu9wJ8IQ== X-Google-Smtp-Source: AA0mqf7IYIFC0nrrLxWx3CYbrAOfLSs9WvGTPe99+1LOYnJ/1kvb+gbKpAZZNbbjxGDPie9vDvZlag== X-Received: by 2002:a5d:4e49:0:b0:242:d4f:961 with SMTP id r9-20020a5d4e49000000b002420d4f0961mr12288577wrt.474.1669804189620; Wed, 30 Nov 2022 02:29:49 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id j33-20020a05600c1c2100b003b4ff30e566sm4313570wms.3.2022.11.30.02.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 02:29:49 -0800 (PST) From: Neil Armstrong Date: Wed, 30 Nov 2022 11:29:46 +0100 Subject: [PATCH v2 2/5] dt-bindings: remoteproc: qcom: adsp: document sm8550 adsp, cdsp & mpss compatible MIME-Version: 1.0 Message-Id: <20221114-narmstrong-sm8550-upstream-remoteproc-v2-2-12bc22255474@linaro.org> References: <20221114-narmstrong-sm8550-upstream-remoteproc-v2-0-12bc22255474@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-remoteproc-v2-0-12bc22255474@linaro.org> To: Rob Herring , Bjorn Andersson , Krzysztof Kozlowski , Konrad Dybcio , Amol Maheshwari , Srinivas Kandagatla , Manivannan Sadhasivam , Mathieu Poirier , Andy Gross Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong , Abel Vesa , linux-remoteproc@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This documents the compatible for the component used to boot the aDSP, cDSP and MPSS on the SM8550 SoC. The SM8550 boot process on SM8550 now requires a secondary "Devicetree" firmware to be passed along the main Firmware, and the cDSP a new power domain named "NSP". A third memory domain for the DSM memory zone is also needed for the MPSS PAS bindings. Signed-off-by: Neil Armstrong --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 195 +++++++++++++++++++++ 1 file changed, 195 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml new file mode 100644 index 000000000000..ac1c02ee780c --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam + +description: + Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + - qcom,sm8550-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + memory-region: + minItems: 2 + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + - description: DSM Memory region + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + maxItems: 2 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 3 + + - if: + properties: + compatible: + enum: + - qcom,sm8550-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm8550-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + power-domain-names: + items: + - const: cx + - const: mxc + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + - description: NSP power domain + power-domain-names: + items: + - const: cx + - const: mxc + - const: nsp + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + remoteproc@30000000 { + compatible = "qcom,sm8550-adsp-pas"; + reg = <0x030000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>, <&dtb_adsp_mem>; + + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + + power-domains = <&rpmhpd_sm8550_lcx>, + <&rpmhpd_sm8550_lmx>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + };