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[2001:14ba:a302:5f12::1]) by smtp.gmail.com with ESMTPSA id be34-20020a056512252200b0049e9122bd1bsm2869082lfb.164.2022.11.23.02.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 02:44:47 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Johan Hovold , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: [PATCH v9 4/4] arm64: dts: qcom: use UFS symbol clocks provided by PHY Date: Wed, 23 Nov 2022 12:44:43 +0200 Message-Id: <20221123104443.3415267-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> References: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove manually created symbol clocks and replace them with clocks provided by PHY. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 ++++--------------------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 15 +++++++++++++-- 3 files changed, 21 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c0a2baffa49d..935ba6e6bc15 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -699,7 +699,9 @@ gcc: clock-controller@300000 { <&pciephy_1>, <&pciephy_2>, <&ssusb_phy_0>, - <0>, <0>, <0>; + <&ufsphy_lane 0>, + <&ufsphy_lane 1>, + <&ufsphy_lane 2>; clock-names = "cxo", "cxo2", "sleep_clk", @@ -2019,6 +2021,7 @@ ufsphy_lane: phy@627400 { reg = <0x627400 0x12c>, <0x627600 0x200>, <0x627c00 0x1b4>; + #clock-cells = <1>; #phy-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a86d9ea93b9d..553cf451f283 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -37,24 +37,6 @@ sleep_clk: sleep-clk { clock-frequency = <32000>; #clock-cells = <0>; }; - - ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; }; cpus { @@ -661,9 +643,9 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <&ufs_phy_rx_symbol_0_clk>, - <&ufs_phy_rx_symbol_1_clk>, - <&ufs_phy_tx_symbol_0_clk>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, <0>, <0>; }; @@ -2147,6 +2129,7 @@ ufs_mem_phy_lanes: phy@1d87400 { <0 0x01d87c00 0 0x1dc>, <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; + #clock-cells = <1>; #phy-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index efb01fefe9c7..95c01391972a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -722,11 +722,21 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_lane>, - <&pcie1_lane>; + <&pcie1_lane>, + <0>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, + <0>; clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk", - "pcie_1_pipe_clk"; + "pcie_1_pipe_clk", + "pcie_1_phy_aux_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; }; gpi_dma2: dma-controller@800000 { @@ -3166,6 +3176,7 @@ ufs_mem_phy_lanes: phy@1d87400 { <0 0x01d87c00 0 0x1dc>, <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; + #clock-cells = <1>; #phy-cells = <0>; }; };