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[83.9.30.37]) by smtp.gmail.com with ESMTPSA id g22-20020a170906595600b0087221268e49sm6581229ejr.186.2023.01.20.13.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 13:01:26 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Douglas Anderson , Loic Poulain , Neil Armstrong , Rajeev Nandan , Stephen Boyd , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Robert Foss , devicetree@vger.kernel.org Subject: [PATCH 6/8] arm64: dts: qcom: sm8350: Fix DSI PLL size Date: Fri, 20 Jan 2023 22:00:58 +0100 Message-Id: <20230120210101.2146852-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230120210101.2146852-1-konrad.dybcio@linaro.org> References: <20230120210101.2146852-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As downstream indicates, DSI PLL is actually 0x27c and not 0x260- wide. Fix that to reserve the correct registers. Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 22bf6239c757..b09eb8880376 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3041,7 +3041,7 @@ mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,sm8350-dsi-phy-5nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, - <0 0x0ae94900 0 0x260>; + <0 0x0ae94900 0 0x27c>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -3138,7 +3138,7 @@ mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,sm8350-dsi-phy-5nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, - <0 0x0ae96900 0 0x260>; + <0 0x0ae96900 0 0x27c>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll";