From patchwork Thu Jan 26 13:14:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 647656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA5BDC61DA2 for ; Thu, 26 Jan 2023 13:14:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229558AbjAZNOz (ORCPT ); Thu, 26 Jan 2023 08:14:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229730AbjAZNOt (ORCPT ); Thu, 26 Jan 2023 08:14:49 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 107BB6951B for ; Thu, 26 Jan 2023 05:14:26 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id j17so1116437wms.0 for ; Thu, 26 Jan 2023 05:14:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kURYlYVInYs10ttpQnifCsWvtgqKTN58XyXAiFJVJmk=; b=vs1slFZNTRGkGwY5ZeFOhINvWnSjW1vc40xeezY992M/0jOmZt7nXHI2tE5L7o0Qrz oM+FtRVXkUgBpaGuhnQ2R0rHBXR8lNHUs6wP/vwZJC90mKkhDn0fdXYMZoufztAyavnX wmeb06hMn7M3k90MzldwrkM8Hjom1768vdwUI0FgujKowzncPZ29KVmm8hC/p55B6iY+ JHJRpHwMFrAC0Ma44EbWtzTNzDuRtm0uYjMGZt3FpB2pMTIX2PkY568oBdhfFq7lz9e8 zy2/9sJReS+EX1SukT3nPJw6ynSKZe4YeQOln/WQ2aisN0rw7qV2fSRZTpj8UZz+QCza RjFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kURYlYVInYs10ttpQnifCsWvtgqKTN58XyXAiFJVJmk=; b=cGQ0j5YkNIgeZexsYZ2nlXx6+duZ/fdEK9i4pZY25m9tyV3y1gZ5ecoeZYNvGCXaZz ctlJ+eF8oZuHaVQGuiqqw8Lxy+I0sUOVO3u995LVWSJ9YXp31ie3qDgv6T18PCOkxPry s9oL+twfdd+GwYKnPtAezK1ZHfMVRjn4Dr6FAO4ZF/w6Eel5srqC2R8BnJX6OrG/vlHy H3O+M1pOEqOkHR9wConq0fBwj9tO4F20l5sD5+EiD9OJAsr0g//+p4y6d/hTlrZapCFA +2DeDTJNwiPqbu3i0MgG19QtgQq+s3K9k/svFC0oJIlzCdzSPs7oT8x99Nay84uzdExo SO/w== X-Gm-Message-State: AFqh2kq4TDMyLECKt4Nr/rNcs781ZiiD9yMH4a8Rd45ukiJAXYIWKoao ekC9CWV34icpV5RxDqTezfF7qg== X-Google-Smtp-Source: AMrXdXv+ghquWRGE3xNz4KO4cOKPUTQqObA+pw5nBQgCK3ILLX6+jVZ3nO09LURQ+7dULPfTOg1wQA== X-Received: by 2002:a05:600c:35c1:b0:3db:1424:e781 with SMTP id r1-20020a05600c35c100b003db1424e781mr29987079wmq.23.1674738864516; Thu, 26 Jan 2023 05:14:24 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c26d200b003da28dfdedcsm1719804wmv.5.2023.01.26.05.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:14:24 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v3 4/8] phy: qcom-qmp: pcs-usb: Add v6 register offsets Date: Thu, 26 Jan 2023 15:14:11 +0200 Message-Id: <20230126131415.1453741-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126131415.1453741-1-abel.vesa@linaro.org> References: <20230126131415.1453741-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa --- The v2 version of this patch was here: https://lore.kernel.org/all/20230126124651.1362533-5-abel.vesa@linaro.org/ Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 + .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h | 31 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 521ea3ce6b83..14d12d198d87 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -26,6 +26,7 @@ #include "phy-qcom-qmp-pcs-misc-v3.h" #include "phy-qcom-qmp-pcs-usb-v4.h" #include "phy-qcom-qmp-pcs-usb-v5.h" +#include "phy-qcom-qmp-pcs-usb-v6.h" /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h new file mode 100644 index 000000000000..9510e63ba9d8 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_ +#define QCOM_PHY_QMP_PCS_USB_V6_H_ + +/* Only for QMP V6 PHY - USB3 have different offsets than V5 */ +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4 +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8 +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8 +#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc +#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90 +#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc +#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec + +#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18 +#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c +#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 +#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44 + +#endif