From patchwork Thu Feb 2 12:38:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 650294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD9DAC61DA4 for ; Thu, 2 Feb 2023 12:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231775AbjBBMjU (ORCPT ); Thu, 2 Feb 2023 07:39:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231644AbjBBMjS (ORCPT ); Thu, 2 Feb 2023 07:39:18 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A908CA16 for ; Thu, 2 Feb 2023 04:39:17 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id q5so1623988wrv.0 for ; Thu, 02 Feb 2023 04:39:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RBMDlVycO88mk4Wf22jm8g0+L2Ufy3vv+GvtkJwrjQU=; b=hqlKJZ/XDnAGNvA277xfk9yQ3k1iXev0ehEqfLPZLaFhdihS9FWNqdmE/HEnFjb6Zg 133k+ycYe9pGig4HDIbT4kb9fbhuD7Tufz6Io3VSRjqSsqRVEe4RDAEAJgnDEdkqYBUh H9ySG/MBuy3dV4p5/LG85+MY93mxFOrgFPNOnO+HqBzf9vIrsz/CWz1fyuSlHNdAGDka yX9X6GihatDIhWnLBQXdhfK5BDBs3atPF0Jwmr3d6OtwjasS4ZzOEUfFDtYy1jICR6Dg YbKPKUJx9qNQbJfrxrkbzAeUG4pPhR5DeQbQCqrGUGhDQwdZsnLCX+EcSw9Zht4GkPAT ozHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RBMDlVycO88mk4Wf22jm8g0+L2Ufy3vv+GvtkJwrjQU=; b=j/L6L/Wx5zWzMVS1Oe/MT1/YY4krDkMJ4Pn/wPtKc4jYh4uD4/o+MH1XGYLJt3sUwU wVqX5+ehg68qx1zHuJNowlfkm05Oa9uzuVVDX7vMjHiXm4pNtjpSkhvBkmu7mTK6FcOx aXQC3gnS46nuqvBaYehUUCVaRzAbQcjzzr8j8DWMZYezhhP+1dtcjT0ZY+QmHtOtFyX7 hv8nCbK0n2HM1JHZIrey0eedRU902k3aNEn7dDD+Jdy50MQFsdqyDy1gxevm9N5kl6p/ /QUuRLOOZ0wYyDhn7ANNNbLoYAn/0E6PlP2LUR2NpqwqkZX/0QeLww/J3Di4A9Aiw3hj qjrQ== X-Gm-Message-State: AO0yUKWQpo5eNtzC9cRo4725p7prDvHMTPgERveWWNYtYRDS6vB2kGt1 s1b3yWgajv2UCPEo4Nuwvsk+Tw== X-Google-Smtp-Source: AK7set8TdQenHIIRITgNdybZLunqgxLiXVKAWN2ckD/8JqgLmNIP+/1q10q1NJADzZkS26T8v7KC1w== X-Received: by 2002:a05:6000:10f:b0:2bf:bf36:1604 with SMTP id o15-20020a056000010f00b002bfbf361604mr5143028wrx.35.1675341555811; Thu, 02 Feb 2023 04:39:15 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id j5-20020adff005000000b002bddd75a83fsm19525644wro.8.2023.02.02.04.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 04:39:15 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Dmitry Baryshkov Subject: [PATCH v6 03/12] phy: qcom-qmp: pcs: Add v6.20 register offsets Date: Thu, 2 Feb 2023 14:38:53 +0200 Message-Id: <20230202123902.3831491-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202123902.3831491-1-abel.vesa@linaro.org> References: <20230202123902.3831491-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v5 of this patch is: https://lore.kernel.org/all/20230124124714.3087948-4-abel.vesa@linaro.org/ Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 ++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 2 files changed, 20 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h new file mode 100644 index 000000000000..9c3f1e4950e6 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_20_H_ +#define QCOM_PHY_QMP_PCS_V6_20_H_ + +/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 +#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 +#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc +#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0 +#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8 +#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 80e3b5c860b6..760de4c76e5b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -40,6 +40,8 @@ #include "phy-qcom-qmp-pcs-v6.h" +#include "phy-qcom-qmp-pcs-v6_20.h" + /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 #define QPHY_V3_DP_COM_SW_RESET 0x04