From patchwork Thu Feb 2 12:38:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 650292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 046F9C61DA4 for ; Thu, 2 Feb 2023 12:39:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232193AbjBBMjs (ORCPT ); Thu, 2 Feb 2023 07:39:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231766AbjBBMjd (ORCPT ); Thu, 2 Feb 2023 07:39:33 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A5538D436 for ; Thu, 2 Feb 2023 04:39:22 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id a2so1298609wrd.6 for ; Thu, 02 Feb 2023 04:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0B2yuqpUAr3hk6ptdpys+Q3pB/tCrjYURP36RVktnLY=; b=PcMhG/5EHIT8pT+dwLYZnfp2D+Wu51YdIpMkO4b9TDz0dGzJTTdTw/xNxIzFh5V8YL o6bIUo/XO8+QXED+GtL5h08min/ApH1BC9sNI6rDgFI7LJWx8z7zKFGG/vQ24xmSQraw YMQ/+zb1nQT3n9/bCI4Kqv7Uhk/rd3T75ZAiLYIhRHFmJQkLyz8YjLxkWEBbixDLRgnT Pdl+A2tgTX3peokdD+0uu6aiulSmUjkL4xPIgwhk31ORu4YsSs7jr17ROrQYHFr7Q7V1 CAzGqDbu9ZMc5TDkycdEFYCwjYmQBDFVCgZp9tG1NEcAMVqE59LzJy9eXi/lMz9JqMgq bJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0B2yuqpUAr3hk6ptdpys+Q3pB/tCrjYURP36RVktnLY=; b=XOja34RTR5g8SvlFHLjvn2kQ3wu1PIeLaPsO9UEUnrJ6RndlaVJnxXN7j3QPSRq2w4 VE5yVhSSBdlqIzj2O7LvG9W14vDa3jmismBmuaRwF+FIc2eHAqlTeiChxUiiwQQka9Mx HxLOtYQ3uanHF+VXKrky9cm7846B2OI/9+lC4fhuZYa0hzHZvF+pi4y0HqVWn8/rd/F6 XmMExVKgYkl9EWIvAonglx/mbKQPEAA6GeZ8pGBmHDYMGWXw62hmVd6cB42fatJEgm44 7WBZWACylNqE8tVWz8kq3BHZlpQUS00Lxdy5Lbi9XJL2HLiaUvTEfly2Q+cshhSGZvhS 5Jmg== X-Gm-Message-State: AO0yUKUJfqS133yHsq2CuKtpfmWBqqAqlLppMGTSLw8zDSe2LEiruXQc HRJq2SLe9tgqQbDl2FnBA9y/BA== X-Google-Smtp-Source: AK7set/WnmOw78Xf7tU01XvxTZd9yTQ+P7f4xl3t8ZpiXAiUXfCWNeNFgtYOgI/mx5BKJuE8pWmZuA== X-Received: by 2002:adf:f7c9:0:b0:2bf:c530:329e with SMTP id a9-20020adff7c9000000b002bfc530329emr5124958wrq.14.1675341560151; Thu, 02 Feb 2023 04:39:20 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id j5-20020adff005000000b002bddd75a83fsm19525644wro.8.2023.02.02.04.39.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 04:39:19 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Dmitry Baryshkov Subject: [PATCH v6 06/12] phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets Date: Thu, 2 Feb 2023 14:38:56 +0200 Message-Id: <20230202123902.3831491-7-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202123902.3831491-1-abel.vesa@linaro.org> References: <20230202123902.3831491-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v5 of this patch is: https://lore.kernel.org/all/20230124124714.3087948-7-abel.vesa@linaro.org/ Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested .../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 2 files changed, 46 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h new file mode 100644 index 000000000000..5385a8b60970 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ + +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac +#define QSERDES_V6_20_TX_LANE_MODE_1 0x78 +#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c +#define QSERDES_V6_20_TX_LANE_MODE_3 0x80 + +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c +#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 +#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 +#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c +#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0 +#define QSERDES_V6_20_RX_DFE_3 0xb4 +#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 +#define QSERDES_V6_20_RX_GM_CAL 0x10c +#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120 +#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148 +#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188 +#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194 +#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc +#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4 +#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8 +#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc +#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200 +#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204 +#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208 +#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c +#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210 +#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214 +#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218 +#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c +#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220 +#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224 +#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 760de4c76e5b..e5974e6caf51 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -23,6 +23,7 @@ #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6_20.h" #include "phy-qcom-qmp-qserdes-pll.h"