From patchwork Thu Feb 2 12:38:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 649740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 584CAC636D4 for ; Thu, 2 Feb 2023 12:39:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232119AbjBBMjk (ORCPT ); Thu, 2 Feb 2023 07:39:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231936AbjBBMjc (ORCPT ); Thu, 2 Feb 2023 07:39:32 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 097748D433 for ; Thu, 2 Feb 2023 04:39:22 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id d14so1564930wrr.9 for ; Thu, 02 Feb 2023 04:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1w7SzdSxf9URmaB5hkVrzDs5tDov2JgjGMJAmtV7+70=; b=kIZRD4reLB+mc4evAc8fbo7WkOW9iWLnC3euuJkHxrnIqSg3mh+bEheyGinQUK91af l5qf7Xpm3Lkz6n5VhybNMDZqfr5AhY/DOSq8nFhaHMrHu2IOGDhLxQ77haqTJpM0tPJR XpGlIRc5VVohYpAvwjFuSCxQiKzPsg1tpvd4lNZr2g+INL++a+237YNyXeplgGD2ivkc 22eShZxs1M+ChfNUTRPjMAJqoHr1E5vWycQYsv8puzCYLZ+p+4sVkebx8ey+3vT9L8rO szGaQ8oKXi2HDafxIAVefl6c1Y1JnkHqr45P5gFbm5p32H2HgEdXIebs4w7pK5t9YMq9 gmFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1w7SzdSxf9URmaB5hkVrzDs5tDov2JgjGMJAmtV7+70=; b=Zju+qs2IDLsxGJYfzYYj3eYZ0rk9ZGdrZuR6wSUTkd89FiJWsDEZcsZv4SyixA0RZJ TLZWIhygTepLXSljExlniuqXBN24EOD+5kzDENzrCETAXH80Sa0+1lrWaytrPURH4Dqd fSy1Ea184SGt7UIFyX0ZbfDiV+CmOtl9FT9JqBDGYLSfTnSAyYOlqDCpj2Q7BCmuTavj wtAPsw9eYFAB6+DG8EvJQpGd/FOr9Xtbzl/5FbXm5L6023Shlik77p5z+Q7glPgGBVAv XYVkfUblrIlWCGUxEC0tTIyUJ3t3wjGzi2FwQchH32OaZEA9WJ+lqs7kGmUgmqL0DJpa sNIQ== X-Gm-Message-State: AO0yUKXGLs8xFc01K1zCW4pHo9/3eVWtq6N2/i/nlVPzUtadtY9jlS/X tJgn9Ug65UEFxA24jnhwlwbnSw== X-Google-Smtp-Source: AK7set9ostxXG76CnJATj+W/i7fwoiZ7QBJtM/ST85kuQxh6EB+1APcC1vwxkvtfjpmhFBYzORUboA== X-Received: by 2002:adf:a202:0:b0:2bf:ec8b:3a5 with SMTP id p2-20020adfa202000000b002bfec8b03a5mr5782970wra.46.1675341561567; Thu, 02 Feb 2023 04:39:21 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id j5-20020adff005000000b002bddd75a83fsm19525644wro.8.2023.02.02.04.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 04:39:21 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v6 07/12] phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets Date: Thu, 2 Feb 2023 14:38:57 +0200 Message-Id: <20230202123902.3831491-8-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202123902.3831491-1-abel.vesa@linaro.org> References: <20230202123902.3831491-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v5 of this patch is: https://lore.kernel.org/all/20230124124714.3087948-8-abel.vesa@linaro.org/ Changes since v5: * none Changes since v4: * none Changes since v3: * none Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested .../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 2 files changed, 33 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h new file mode 100644 index 000000000000..86d7d796d5d7 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ +#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ + +#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0 +#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0 +#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c +#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index e5974e6caf51..148663ee713a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -24,6 +24,7 @@ #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v6_20.h" +#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h" #include "phy-qcom-qmp-qserdes-pll.h"