From patchwork Wed Feb 8 18:00:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 651757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91B69C636CC for ; Wed, 8 Feb 2023 18:01:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231866AbjBHSBM (ORCPT ); Wed, 8 Feb 2023 13:01:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231688AbjBHSA7 (ORCPT ); Wed, 8 Feb 2023 13:00:59 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FBA2530EA for ; Wed, 8 Feb 2023 10:00:55 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id z13so6442143wmp.2 for ; Wed, 08 Feb 2023 10:00:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cig8x+DASIoHgM0lhJw7c8nOcZnMIzVBIm4rhxwpdQI=; b=CFD/xtGvafnWR1KJaRW8segO0sG7bJ5FIA728XF3pLAoWhWoR6LZRuCHW9zCIMzkve 4Fu4+g/n8aHdItfBkLytj3damxBVW/ydd8KN3ZonBQ8Nl9LZ8mPcFQz+O5ygcPqQv/Ch qGl7hSXTKYV8IyKkZHzM1ZOWlpeZlcKGsVzw4jN7w6I8bKZsZIk/TYTMIHtaty0Rprtv 4HgfvGr4s7NjPQeCmZdGeki3qqaFgPEs2uRTQNfzQ2wBograY43MB8ikihGAiyEpvh6P MKFH9/Y/CkXW3Gqy2qhnjJwuHS5A87EV6r5Urb0djsKwPxXxnBY6eIT45QlqD7DNOMqF 1bdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cig8x+DASIoHgM0lhJw7c8nOcZnMIzVBIm4rhxwpdQI=; b=PCdhZqH6OPTGhuCIUvvehkxJNq86oJz3v4ZVroAKC4fOqHO6W+ZQEMsabX0kIYzEBA QJxUJRrgVXGELq7dI+iD8ZHcpldWrh7HClQBkRgBpZSg2TLaD6aYQKlp2ymANY6lhASN Ap5nQFdDofLsSjNUhOA2ZZ9mS0vUbHvj2erZ/TxMLbVqUR3JSS5g320f6odmMxRB9Hu7 NF4e+yqpThIKU5EhjnrZQoW6c3GjwgG4DyywqXufNMcZPs4nQbsCVp+tZFhfBlFHgu94 9cITDYizJAqOzjBR5yke3Sq7annBoXR2zTrufRLBeBVbCJSuitFsbJMsJYv9xQpjvZuR FhFg== X-Gm-Message-State: AO0yUKWKxa6Tc4TxFGBiyZVz9UCriIbrec0AEFCqsqdgR2JkNRwnuxLC mrIrgCw0I6Ezj3fnN6U4JAo9og== X-Google-Smtp-Source: AK7set+uevGCDjXBaJSX7rfNlRHkcHw4RM/U9dJZVW5UCbgj8UF1zockXk7XELN2l+TE9mZ5nN41Kw== X-Received: by 2002:a05:600c:502b:b0:3db:2e6e:7826 with SMTP id n43-20020a05600c502b00b003db2e6e7826mr9884278wmr.5.1675879255176; Wed, 08 Feb 2023 10:00:55 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id k20-20020a05600c169400b003dc54eef495sm2370286wmn.24.2023.02.08.10.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Feb 2023 10:00:54 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Dmitry Baryshkov Subject: [PATCH v9 05/11] phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets Date: Wed, 8 Feb 2023 20:00:14 +0200 Message-Id: <20230208180020.2761766-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230208180020.2761766-1-abel.vesa@linaro.org> References: <20230208180020.2761766-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- The v8 of this patch is: https://lore.kernel.org/all/20230206212619.3218741-6-abel.vesa@linaro.org/ Changes since v8: * none Changes since v7: * none Changes since v6: * none Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 +++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 05b59f261999..907f3f236f05 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -30,6 +30,7 @@ #include "phy-qcom-qmp-pcs-pcie-v5.h" #include "phy-qcom-qmp-pcs-pcie-v5_20.h" #include "phy-qcom-qmp-pcs-pcie-v6.h" +#include "phy-qcom-qmp-pcs-pcie-v6_20.h" #include "phy-qcom-qmp-pcie-qhp.h" /* QPHY_SW_RESET bit */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h new file mode 100644 index 000000000000..e3eb08776339 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ + +/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 +#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184 +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c +#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac +#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0 + +#endif