@@ -375,7 +375,7 @@ pcie_rc: pcie@1c00000 {
power-domains = <&gcc PCIE_GDSC>;
- phys = <&pcie_lane>;
+ phys = <&pcie_phy>;
phy-names = "pciephy";
status = "disabled";
@@ -422,7 +422,7 @@ pcie_ep: pcie-ep@1c00000 {
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
- phys = <&pcie_lane>;
+ phys = <&pcie_phy>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
@@ -432,18 +432,25 @@ pcie_ep: pcie-ep@1c00000 {
pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
- reg = <0x01c07000 0x1c4>;
+ reg = <0x01c07000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
- <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+ <&gcc GCC_PCIE_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
- "refgen";
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";
@@ -452,20 +459,6 @@ pcie_phy: phy@1c07000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie_lane: lanes@1c06000 {
- reg = <0x01c06000 0x104>, /* tx0 */
- <0x01c06200 0x328>, /* rx0 */
- <0x01c07200 0x1e8>, /* pcs */
- <0x01c06800 0x104>, /* tx1 */
- <0x01c06a00 0x328>, /* rx1 */
- <0x01c07600 0x800>; /* pcs_misc */
- clocks = <&gcc GCC_PCIE_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
- clock-output-names = "pcie_pipe_clk";
- };
};
ipa: ipa@1e40000 {
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm/boot/dts/qcom-sdx55.dtsi | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-)