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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f4-20020a2e3804000000b0029ad1fc89b3sm5189658lja.60.2023.03.29.12.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 12:17:37 -0700 (PDT) From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:17:28 +0200 Subject: [PATCH 1/4] arm64: dts: qcom: msm8998: Improve GPU OPP table MIME-Version: 1.0 Message-Id: <20230329-topic-adreno_opp-v1-1-24d34ac6f007@linaro.org> References: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> In-Reply-To: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Jordan Crouse , Srinivas Kandagatla , Vivek Gautam , Vinod Koul , Rob Clark , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680117452; l=3231; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BuTOgjCT81kJFbrqBabPtOTaRvqV7WCYi0kTMwbrGyM=; b=sIueiwaBv29WZYicIP/gR6f1I5FJrtIi4R/EoqLoj5R6f4Cpwk3nADWHqIKjdyJsZQNZ5nsG2rgH BOk3yWWuDdxPFGzt0xsYbCEE08QXV0aCsCc9Zw/ZrDReYpsf8AdS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a newline before the first OPP subnode, remove useless opp-supported-hw (there's only a single speed bin anyway) and replace opp-level with required-opps to make sure the power domain level is actually set, as opp-level is not the right property for this.. Furthermore, correct the levels that were incorrect before (confirmed against downstream). Round off frequencies that had uneven fluff on the last two digits. To top if off, leave a note that we should really be scaling the VDD GFX power domain coming from CPR4, which is not yet supported. Scaling MX is still very important though and can be considered valid for the time being - it's better if we scale at one of two voltage rails than if we scaled none.. Fixes: 87cd46d68aea ("arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 09b222f363c2..11952f9ed9ae 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1396,51 +1396,46 @@ adreno_gpu: gpu@5000000 { interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; + /* TODO: also scale VDDGFX with CPR4 */ power-domains = <&rpmpd MSM8998_VDDMX>; status = "disabled"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; - opp-710000097 { - opp-hz = /bits/ 64 <710000097>; - opp-level = ; - opp-supported-hw = <0xff>; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + required-opps = <&rpmpd_opp_turbo>; }; - opp-670000048 { - opp-hz = /bits/ 64 <670000048>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + required-opps = <&rpmpd_opp_turbo>; }; - opp-596000097 { - opp-hz = /bits/ 64 <596000097>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + required-opps = <&rpmpd_opp_nom>; }; - opp-515000097 { - opp-hz = /bits/ 64 <515000097>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + required-opps = <&rpmpd_opp_nom>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; }; };