From patchwork Wed Mar 29 08:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 669022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E0DEC77B6F for ; Wed, 29 Mar 2023 08:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229656AbjC2IsY (ORCPT ); Wed, 29 Mar 2023 04:48:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231194AbjC2IsW (ORCPT ); Wed, 29 Mar 2023 04:48:22 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 985C31721; Wed, 29 Mar 2023 01:48:21 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T8XJud030690; Wed, 29 Mar 2023 08:47:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=k9Zd+poeSAflCAm6BhMQn4MEZzgfoY/iIo3aPnSnmIs=; b=pVCB/fpBxCXIqJqhxmmZDwyeCUIE8UDx+VJSQ5512bpoyHMxxnRUDrKbHwJrwSUSVVfx uhzS7WQUiO+Ezlxpn7hSnONyuvrS/6roJCovs5jEubmh9rOaLa8EQz/zBFeXkf7SqhVM rXkQ1EP2+NFrZ0De2DIYbmJxG/tnQ15qwGBbsXP19Wb5larpXVVfeCW0DHyVngpG/f0f ikk8Abapg5GxX+O1VenxCpAE+XdASqsYp8HETmHyVSyu1HgE3JxZOrSBG/uxpvCANCrw Fm9cUs7WwLvoXgUYN3746fYe/C6dndKxdZadbUXFLIk31aUr2x+6pV0V4CfqKc8sh6HI 6A== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmawsgw0w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:59 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T8lwTo009168 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 08:47:58 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:58 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 6/8] dt-bindings: arm: Add support for TPDM CMB MSR register Date: Wed, 29 Mar 2023 01:47:42 -0700 Message-ID: <20230329084744.5705-7-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: y-wAyoBk0j0UeFbxH7lhCOezIDlnpzmA X-Proofpoint-ORIG-GUID: y-wAyoBk0j0UeFbxH7lhCOezIDlnpzmA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 mlxlogscore=970 malwarescore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) for TPDM. It specifies the number of CMB MSR registers supported by the TDPM. Signed-off-by: Mao Jinlong --- .../devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 691c7ba365aa..283dfb39d46f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -62,6 +62,15 @@ properties: minimum: 0 maximum: 32 + qcom,cmb-msr-num: + description: + Specifies the number of CMB MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 128 + clocks: maxItems: 1 @@ -97,6 +106,7 @@ examples: qcom,dsb-element-size = <32>; qcom,dsb_msr_num = <16>; + qcom,cmb-msr-num = <6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk";