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[83.9.2.185]) by smtp.gmail.com with ESMTPSA id h11-20020a2eb0eb000000b002b6cc17add3sm2431483ljl.25.2023.08.08.14.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 14:02:56 -0700 (PDT) From: Konrad Dybcio Date: Tue, 08 Aug 2023 23:02:43 +0200 Subject: [PATCH v2 05/14] drm/msm/a6xx: Introduce a6xx_llc_read MIME-Version: 1.0 Message-Id: <20230628-topic-a7xx_drmmsm-v2-5-1439e1b2343f@linaro.org> References: <20230628-topic-a7xx_drmmsm-v2-0-1439e1b2343f@linaro.org> In-Reply-To: <20230628-topic-a7xx_drmmsm-v2-0-1439e1b2343f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1691528566; l=1048; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=TnlFTvDdHhoi4rVAYZ2tyAwm56dDVRIuWBaJyWSlozw=; b=a/SUmHuwx6GbHQKZ+zB6XePPj9sI9E9dNkhNkm4geJQBC/XMyObKFtFrnDWlvJ+i/rulMyMRt UaeyhJm1kS7BUbCC3ZrXmWHAvbWEMsshMCIBeYdQFx+cLTGdOsb1k+7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a helper that does exactly what it says on the can, it'll be required for A7xx. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1ed202c4e497..0fef92f71c4e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1740,6 +1740,11 @@ static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); } +static u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) +{ + return msm_readl(a6xx_gpu->llc_mmio + (reg << 2)); +} + static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) { msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));