From patchwork Fri Jul 14 01:55:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 702832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3DF5C0015E for ; Fri, 14 Jul 2023 01:55:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232823AbjGNBzJ (ORCPT ); Thu, 13 Jul 2023 21:55:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232624AbjGNBzJ (ORCPT ); Thu, 13 Jul 2023 21:55:09 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AC2F2D64 for ; Thu, 13 Jul 2023 18:55:07 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4fb7dc16ff0so2377661e87.2 for ; Thu, 13 Jul 2023 18:55:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689299705; x=1689904505; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jPcgkOPls48kOZUuhjs762Sf1Fh9cTy88sR434ar5b0=; b=jcsx+2FBDnPPc58g8YDZ1jsQiT/RaBx51fAPmLr91QmOz9c5gxzV4zZ4ZjetGMNY2H G7q63XHIS353BAibbUrgBAGlSG2prj/tF1L3dTgIqYP5phALYy+BkkwynvRTdPKYhphh T7NzqFP6mo8LNcMvF2Znh+uE/bSRnEHvb/PjxDK8cJCJDr7a8b7MDO9QsecG/AL5nfLe CmZUVIFDdDJAxVxaofkVGA4JWJjHeUdkv4I/sAIJsvQewsz/aM6qhObmFPzybe6LYPwa fmiRKOGP76oxO1D16hI/MAVA1AuOkPFQSYESLdF1DuuPn6q9LvqknQRUiQtQa/r6cdLl UBsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689299705; x=1689904505; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jPcgkOPls48kOZUuhjs762Sf1Fh9cTy88sR434ar5b0=; b=UqtAkU4VyrhDEfkcp71hEULdditWQybscZWYAnwYi6YHGKpTPuOn7lW71U/Gb591pr 6AE7NZYmiJNLQZGGfZpVZfQw/CoH7P/ZNPMux1WpM0uVQOT6OzIMBWfB6KMisJZYDLEH QUJ8I0PaMl6mT2HxUyLH5ML4wcyVCq545cn0cTylfdtNJH3AI/523K5mc1m1n/2w3fqS MdhbN8tfQrxUU/1FxEM5lkmAOJzTbqIYTFw6gGrLKHA4kQy/dZIQmgCZCDqCe6QKlDFt R5gXsbOhEFzAtZyQMLpIoLmqVIr772izCeXkmeU2Zep/vYdDsnNp5I/74ooVrUWprA00 rFxw== X-Gm-Message-State: ABy/qLb/OP7uZPveVdAneH1GxqbvYS8IP9zMvbSI1VTLogfDdDuWFfuw nRz9LwvycvD28tyVzGKbEYdL0Q== X-Google-Smtp-Source: APBJJlE9xEH0dTBoAM8EChNeAUnOL40zKh11xvYu9/hVUcJH1W8OHfLu1HLb8XXPuDcQdWqf6THuXA== X-Received: by 2002:a19:4f1b:0:b0:4f7:6966:36fb with SMTP id d27-20020a194f1b000000b004f7696636fbmr2155697lfb.12.1689299705541; Thu, 13 Jul 2023 18:55:05 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id q8-20020ac25148000000b004f3afa1767dsm1297550lfd.197.2023.07.13.18.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 18:55:05 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 2/4] drm/msm/dpu: drop the `smart_dma_priority' field from struct dpu_sspp_sub_blks Date: Fri, 14 Jul 2023 04:55:01 +0300 Message-Id: <20230714015503.3198971-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230714015503.3198971-1-dmitry.baryshkov@linaro.org> References: <20230714015503.3198971-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation to deduplicating SSPP subblocks, drop the (unused) `smart_dma_priority' field from struct dpu_sspp_sub_blks. If it is needed later (e.g. for SmartDMA v1), it should be added to the SSPP declarations themselves. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 68 +++++++++---------- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 - 2 files changed, 32 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index daec3f2758e3..63304c2ee6d9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -251,11 +251,10 @@ static const uint32_t wb2_formats[] = { *************************************************************/ /* SSPP common configuration */ -#define _VIG_SBLK(sdma_pri, qseed_ver) \ +#define _VIG_SBLK(qseed_ver) \ { \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ - .smart_dma_priority = sdma_pri, \ .scaler_blk = {.name = "scaler", \ .base = 0xa00, .len = 0xa0,}, \ .csc_blk = {.name = "csc", \ @@ -267,11 +266,10 @@ static const uint32_t wb2_formats[] = { .rotation_cfg = NULL, \ } -#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \ +#define _VIG_SBLK_ROT(qseed_ver, rot_cfg) \ { \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ - .smart_dma_priority = sdma_pri, \ .scaler_blk = {.name = "scaler", \ .base = 0xa00, .len = 0xa0,}, \ .csc_blk = {.name = "csc", \ @@ -283,11 +281,10 @@ static const uint32_t wb2_formats[] = { .rotation_cfg = rot_cfg, \ } -#define _DMA_SBLK(sdma_pri) \ +#define _DMA_SBLK \ { \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ - .smart_dma_priority = sdma_pri, \ .format_list = plane_formats, \ .num_formats = ARRAY_SIZE(plane_formats), \ .virt_format_list = plane_formats, \ @@ -295,13 +292,13 @@ static const uint32_t wb2_formats[] = { } static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = - _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = - _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = - _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = - _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { .rot_maxheight = 1088, @@ -310,64 +307,63 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { }; static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = - _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = - _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = - _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = - _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK; +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK; +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK; +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK; static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = - _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = - _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); + _VIG_SBLK_ROT(DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = - _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = - _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED3LITE); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = - _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = - _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = - _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = - _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = - _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = - _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = - _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = - _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); -static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); + _VIG_SBLK(DPU_SSPP_SCALER_QSEED4); +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK; +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK; -#define _VIG_SBLK_NOSCALE(sdma_pri) \ +#define _VIG_SBLK_NOSCALE \ { \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ - .smart_dma_priority = sdma_pri, \ .format_list = plane_formats_yuv, \ .num_formats = ARRAY_SIZE(plane_formats_yuv), \ .virt_format_list = plane_formats, \ .virt_num_formats = ARRAY_SIZE(plane_formats), \ } -static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2); -static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1); +static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE; +static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK; /************************************************************* * MIXER sub blocks config diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4e8fc3bbc240..cc1800e324dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -392,7 +392,6 @@ struct dpu_caps { * common: Pointer to common configurations shared by sub blocks * @maxdwnscale: max downscale ratio supported(without DECIMATION) * @maxupscale: maxupscale ratio supported - * @smart_dma_priority: hw priority of rect1 of multirect pipe * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps * @qseed_ver: qseed version * @scaler_blk: @@ -406,7 +405,6 @@ struct dpu_caps { struct dpu_sspp_sub_blks { u32 maxdwnscale; u32 maxupscale; - u32 smart_dma_priority; u32 max_per_pipe_bw; u32 qseed_ver; struct dpu_scaler_blk scaler_blk;