From patchwork Wed Jul 19 04:14:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 705423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6D3BC001DF for ; Wed, 19 Jul 2023 04:16:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbjGSEQi (ORCPT ); Wed, 19 Jul 2023 00:16:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230339AbjGSEQW (ORCPT ); Wed, 19 Jul 2023 00:16:22 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A43231996; Tue, 18 Jul 2023 21:15:58 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J3JTKQ016619; Wed, 19 Jul 2023 04:15:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=+HG0PHpG4Sk3k7Z/cvq3Ox0pIVAq9VNAd1LSvmyrszY=; b=kUZHZa9Vhyctnd44zHQ4zbNcBEOKL6WEWEcj72VoXqePinYEGfErgg0DzxpJLO8XYK84 QHn709uQD9ZL1r8bSBz02dVG+aiCZAAhJG8Lg0R/iUohoMgT6gC/QcFo0R90s/DTIphv fE6KgP+ZisJl/4WlP5DGvIUCzhc2o8WA9AP9Yxt3C0cF0BnCe/6EMqAM+HX2cYzciKGA m143LH/10G3Chxl4F8TWeoww3wPxPDgpFf92oKfwzZiTx0V9Yp1cF80gc97J/PbY92jP 2OaxaUKHktuJHWGOPWjGMNBA0h8uuyPb98nWRCqpCt+Ybvxbk+0xpZI8BXvvVCAgM00x /w== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rwpphjc83-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 04:15:52 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36J4Fplv000933 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 04:15:51 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 18 Jul 2023 21:15:46 -0700 From: Imran Shaik To: Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Bjorn Andersson , Taniya Das , Imran Shaik , "Melody Olvera" , Dmitry Baryshkov , , , , , Jagadeesh Kona , Satya Priya Kakitapalli , Ajit Pandey Subject: [PATCH V4 6/7] clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops Date: Wed, 19 Jul 2023 09:44:49 +0530 Message-ID: <20230719041450.737929-7-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230719041450.737929-1-quic_imrashai@quicinc.com> References: <20230719041450.737929-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gdEcI83EUPAhBWXamCxC9CnYBJc8gNS5 X-Proofpoint-ORIG-GUID: gdEcI83EUPAhBWXamCxC9CnYBJc8gNS5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_01,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 impostorscore=0 spamscore=0 clxscore=1011 bulkscore=0 mlxlogscore=899 malwarescore=0 mlxscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190039 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update the GCC SDCC clock RCG ops to floor_ops to avoid the overclocking issues on QDU1000 and QRU1000 SoCs. Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v3: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 718c34dca6e8..540577ae58e4 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { .name = "gcc_sdcc5_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { .name = "gcc_sdcc5_ice_core_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, };