| Message ID | 20230827114519.48797-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names | expand |
On 27.08.2023 13:45, Krzysztof Kozlowski wrote: > Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy": > > arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- drivers/pci/controller/dwc/pcie-qcom-ep.c 549: pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); welp looks like this never worked.. Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 27.08.2023 13:45, Krzysztof Kozlowski wrote: > The SDX65 GCC clock controller expects two required clocks: > pcie_pipe_clk and usb3_phy_wrapper_gcc_usb30_pipe_clk. The first one is > provided by existing phy node, but second is not yet implemented. > > qcom-sdx65-mtp.dtb: clock-controller@100000: clocks: [[11, 0], [11, 1], [12]] is too short > qcom-sdx65-mtp.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too short > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 28/08/2023 11:53, Konrad Dybcio wrote: > On 27.08.2023 13:45, Krzysztof Kozlowski wrote: >> Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy": >> >> arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- > drivers/pci/controller/dwc/pcie-qcom-ep.c > 549: pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); > > welp looks like this never worked.. And if only it could have been spotted with some automated tooling, before posting to LKML... > > > Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP") > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Thanks Best regards, Krzysztof
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 81d018fe7d9b..93c6c80dc379 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -337,7 +337,7 @@ pcie_ep: pcie-ep@1c00000 { power-domains = <&gcc PCIE_GDSC>; phys = <&pcie_phy>; - phy-names = "pcie-phy"; + phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>;
Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy": arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)