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[80.115.237.132]) by smtp.gmail.com with ESMTPSA id i15-20020a1709064ecf00b009a2202bfce5sm6957130ejv.118.2023.08.30.02.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 02:58:43 -0700 (PDT) From: Luca Weiss Date: Wed, 30 Aug 2023 11:58:26 +0200 Subject: [PATCH 01/11] arm64: dts: qcom: sc7280: Mark some nodes as 'reserved' MIME-Version: 1.0 Message-Id: <20230830-fp5-initial-v1-1-5a954519bbad@fairphone.com> References: <20230830-fp5-initial-v1-0-5a954519bbad@fairphone.com> In-Reply-To: <20230830-fp5-initial-v1-0-5a954519bbad@fairphone.com> To: cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Linus Walleij , "Rafael J. Wysocki" , Viresh Kumar Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org With the standard Qualcomm TrustZone setup, components such as lpasscc, pdc_reset and watchdog shouldn't be touched by Linux. Mark them with the status 'reserved' and reeable them in the chrome-common dtsi. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 ++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 2e1cd219fc18..8eb30aa226a2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -46,6 +46,14 @@ wpss_mem: memory@9ae00000 { }; }; +&lpasscc { + status = "okay"; +}; + +&pdc_reset { + status = "okay"; +}; + /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ &pmk8350_pon { status = "disabled"; @@ -84,6 +92,10 @@ &scm { dma-coherent; }; +&watchdog { + status = "okay"; +}; + &wifi { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 042908048d09..98a8d627a348 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2267,6 +2267,7 @@ lpasscc: lpasscc@3000000 { clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; #clock-cells = <1>; + status = "reserved"; }; lpass_rx_macro: codec@3200000 { @@ -4216,6 +4217,7 @@ pdc_reset: reset-controller@b5e0000 { compatible = "qcom,sc7280-pdc-global"; reg = <0 0x0b5e0000 0 0x20000>; #reset-cells = <1>; + status = "reserved"; }; tsens0: thermal-sensor@c263000 { @@ -5212,11 +5214,12 @@ msi-controller@17a40000 { }; }; - watchdog@17c10000 { + watchdog: watchdog@17c10000 { compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; interrupts = ; + status = "reserved"; }; timer@17c20000 {