diff mbox series

[03/11] arm64: dts: qcom: sc7280: Move qfprom clock to chrome-common

Message ID 20230830-fp5-initial-v1-3-5a954519bbad@fairphone.com
State New
Headers show
Series Initial support for the Fairphone 5 smartphone | expand

Commit Message

Luca Weiss Aug. 30, 2023, 9:58 a.m. UTC
On non-ChromeOS boards the clock cannot be touched, so move it in the
chrome-common dtsi which is the only place where it's needed.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 +++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi               | 2 --
 2 files changed, 5 insertions(+), 2 deletions(-)

Comments

Luca Weiss Aug. 31, 2023, 11:28 a.m. UTC | #1
On Wed Aug 30, 2023 at 12:09 PM CEST, Konrad Dybcio wrote:
> On 30.08.2023 11:58, Luca Weiss wrote:
> > On non-ChromeOS boards the clock cannot be touched, so move it in the
> > chrome-common dtsi which is the only place where it's needed.
> > 
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> If that clock is not registered (e.g. it's in protected-clocks = <>,
> would the _optional handler not handle it just fine?

Right, that appears to work!

~ # ls -d /sys/bus/platform/drivers/qcom,qfprom/*.efuse
/sys/bus/platform/drivers/qcom,qfprom/784000.efuse
~ # cat /sys/firmware/devicetree/base/soc@0/efuse@784000/clock-names; echo
core
~ # hexdump -C /sys/firmware/devicetree/base/soc@0/efuse@784000/clocks
00000000  00 00 00 03 00 00 00 b8                           |........|
00000008

Never tested this case before, but since it appears to work with the
patched qfprom driver (other patch in this series) I think we can drop
this patch.
Will also have to adjust some other patches in my local tree then that
do similar things ;)

Regards
Luca

>
> Konrad
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 8eb30aa226a2..6cfcec1eabd9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -59,6 +59,11 @@  &pmk8350_pon {
 	status = "disabled";
 };
 
+&qfprom {
+	clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
+	clock-names = "core";
+};
+
 /*
  * Chrome designs always boot from SPI flash hooked up to the qspi.
  *
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 98a8d627a348..5c78038369fd 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -897,8 +897,6 @@  qfprom: efuse@784000 {
 			      <0 0x00780000 0 0xa20>,
 			      <0 0x00782000 0 0x120>,
 			      <0 0x00786000 0 0x1fff>;
-			clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
-			clock-names = "core";
 			power-domains = <&rpmhpd SC7280_MX>;
 			#address-cells = <1>;
 			#size-cells = <1>;