From patchwork Wed Oct 4 16:44:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 729357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61526E7C4E2 for ; Wed, 4 Oct 2023 16:44:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243474AbjJDQou (ORCPT ); Wed, 4 Oct 2023 12:44:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243473AbjJDQor (ORCPT ); Wed, 4 Oct 2023 12:44:47 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA7E1D8 for ; Wed, 4 Oct 2023 09:44:43 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-692ada71d79so1849773b3a.1 for ; Wed, 04 Oct 2023 09:44:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696437883; x=1697042683; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u4IEC6XCK24n1wITjZREwVBDCFLCyw9ygvF6/hCtGR0=; b=mu5T4V90A9l/3nQeyFk/x/I8Fi9Yng739I3ldXZr6scKwLI1JGnpMeZxOQ8Kif+uA1 DgsHlQ8oUtzoSZ/nl33ZpEHbnPwyenrmvZQyvARj4aCf3B8C7ap6SP518JUfJ2MBUN5g us2zLf8tIMUuL5xP/TTwXwGK+zsjEMZzrmT19CZ3u6BbsAdfF02Zs4OuaFWxM1lJSJjs J8nzLerQhCNSIP9mGv65m+Bh1v6Vs4WP78rnHI1+DrmHRGe8YwT8aasd+7shqrriKboB 1l5aVycV4cxe6xRKO4/fTjk4lt7E1Pob83oc+2EuOf6/or8pJN0iky5i9FbLF2YTjQAI P/WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696437883; x=1697042683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u4IEC6XCK24n1wITjZREwVBDCFLCyw9ygvF6/hCtGR0=; b=G0HIQZpmlc6MLTEj/tsm/cP7OzJsiwYA7NO7iXDm58qaEl0MLM4g3ROxhMMS7GxBAE mO4ZK0qkgdJ/mI9A/8N3p87xlxLaahpxKvUOKfbRS2+RhWLbhx8P9tU7xtIcLmd6Otnp ctxVxRNd54tcbW5BVP1v9+XYpLdAr6v+aU+8c4Dmf1IBgF7sjhDdQ4BI40GvA5mPVVwb GNXdwptLw+Grn3OiLG9p4xzCSMYUkLZ4JeUBEtvw6qlAGnvAHRQq+UKP7TMTr9OUGF/8 ert0fy4Fz9ZpqXEMzuiOm8QcjbuXkwb5MuSw7CjFMwPiVZULBOq+lJV1YO4FCHEtNqJe qYmw== X-Gm-Message-State: AOJu0YzjIjaRkayCfVvjpHTU9S0QEmZ0TS2tccJ0paI8d+w78xgtL4SS DyAAMC4K3Pf0eXrQaGXll0p1 X-Google-Smtp-Source: AGHT+IHzu1GFmgDAo8U93kkM9EidImikgb1LUVvgT5JBzNPFRTay0hk2AB5zES9Tat+W44s87NkG4A== X-Received: by 2002:a05:6a21:329c:b0:15c:b7b9:fc21 with SMTP id yt28-20020a056a21329c00b0015cb7b9fc21mr3263421pzb.14.1696437883311; Wed, 04 Oct 2023 09:44:43 -0700 (PDT) Received: from localhost.localdomain ([117.217.185.220]) by smtp.gmail.com with ESMTPSA id k14-20020aa792ce000000b0066a31111cc5sm3434628pfa.152.2023.10.04.09.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 09:44:43 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 2/3] PCI: qcom-ep: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed Date: Wed, 4 Oct 2023 22:14:29 +0530 Message-Id: <20231004164430.39662-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231004164430.39662-1-manivannan.sadhasivam@linaro.org> References: <20231004164430.39662-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Instead of hardcoding the link speed in MBps, use existing PCIE_SPEED2MBS_ENC() macro that does the encoding of the link speed for us. Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do the conversion to ICC speed. This eliminates the need for a switch case in qcom_pcie_icc_update() and also works for future Gen speeds without any code modifications. Suggested-by: Bjorn Helgaas Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- Changes in v4: * Modified the subject and commit message as per Bjorn's suggestion Changes in v3: - New patch drivers/pci/controller/dwc/pcie-qcom-ep.c | 31 +++++------------------ 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 8bd8107690a6..32c8d9e37876 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -23,6 +23,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" /* PARF registers */ @@ -135,10 +136,8 @@ #define CORE_RESET_TIME_US_MAX 1005 #define WAKE_DELAY_US 2000 /* 2 ms */ -#define PCIE_GEN1_BW_MBPS 250 -#define PCIE_GEN2_BW_MBPS 500 -#define PCIE_GEN3_BW_MBPS 985 -#define PCIE_GEN4_BW_MBPS 1969 +#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ + Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) #define to_pcie_ep(x) dev_get_drvdata((x)->dev) @@ -266,7 +265,7 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci = &pcie_ep->pci; - u32 offset, status, bw; + u32 offset, status; int speed, width; int ret; @@ -279,25 +278,7 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - switch (speed) { - case 1: - bw = MBps_to_icc(PCIE_GEN1_BW_MBPS); - break; - case 2: - bw = MBps_to_icc(PCIE_GEN2_BW_MBPS); - break; - case 3: - bw = MBps_to_icc(PCIE_GEN3_BW_MBPS); - break; - default: - dev_warn(pci->dev, "using default GEN4 bandwidth\n"); - fallthrough; - case 4: - bw = MBps_to_icc(PCIE_GEN4_BW_MBPS); - break; - } - - ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw); + ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); if (ret) dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); @@ -335,7 +316,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) * Set an initial peak bandwidth corresponding to single-lane Gen 1 * for the pcie-mem path. */ - ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS)); + ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret);