From patchwork Thu Oct 5 21:27:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 730424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7893EE92FCB for ; Thu, 5 Oct 2023 21:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229750AbjJEV1N (ORCPT ); Thu, 5 Oct 2023 17:27:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230174AbjJEV1L (ORCPT ); Thu, 5 Oct 2023 17:27:11 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEBC89E for ; Thu, 5 Oct 2023 14:27:10 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-50308217223so1791881e87.3 for ; Thu, 05 Oct 2023 14:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696541229; x=1697146029; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2hPtVzzZO9pBznL56T6VYtPDn+5rPWC88sELbHece2w=; b=ANdQcTP1JlpxhhtGpVF79ZfprXbVtEY1vCIHVVnMzBUzMy95+B/jGjMmLr5SqHwJyH +odA8ODm2GAgmy9CpoliN29IkYTT2WPPn0eIe6kILehQgQ1ZWnzk91lp7rO2f0VsNMb2 +0S9jdD8wBVhLxfuwlt9GHqye0zVWBDw4tupvohKNRoDJKYXcRQWuNJUL4Y07oDDiD60 nSobcKHAX8DWJ7Mi/HgdlayZaRQkplExZo02+5LSIw8PFeGTlymCOBXyLdo+N9zxFg1G Wke+Sq1r05M4K50f+FBI5p/Ij49zaFVQO5hbHhGuUKoQw6ZCeHLQ2/l3CVn7DlmX17Pw GH8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696541229; x=1697146029; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2hPtVzzZO9pBznL56T6VYtPDn+5rPWC88sELbHece2w=; b=mMECcoeHHkMmAqrFVjzUQEMdaZcL0CqR3pFT56gr/IbaBHuWlN3D+kMhaniVG376WX myyit7gjeRzm2tsa2HQDRYl9UpB9ocl7iK7BF7J4TszHmdjAeTyNN+BtVz/R6DaogDPi 9/dj5lhaFKiDuKdVIn3N6pPH4QGebiKvjc+3K2j9oENxJblSlVt/hp0miLw+YgvxMjnD +y4o0z69MNaNGb3mP+gYRs7VvJvuePGrk6n+9dizKpszqcGMI+eRk74snv63IC9VqvJS j10d7PXx/2nxOUkpDcx14FOg3w8sdVBrVW5ngI76H8ChQYKpDt6RelUMYt6G7qiQsnQI tb4w== X-Gm-Message-State: AOJu0YwGCX/xpx81E2OLxNJ2vpNClQ723dmJbWrDmyd4N78qfe8VPzl1 3TsDNaRLuucn9hS2V5p8pvBvuk7ctz2MUi0r00A= X-Google-Smtp-Source: AGHT+IHyWaHI/ccMpMsiZJmgLT39m4mhrH8iEHE1/oJOIFRMc9jb/U/tw82wSvsr5Nrd2WpxJ9ZDFQ== X-Received: by 2002:a19:910d:0:b0:501:ba04:f34b with SMTP id t13-20020a19910d000000b00501ba04f34bmr5308420lfd.44.1696541229128; Thu, 05 Oct 2023 14:27:09 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b00500b3157ec6sm8435lff.143.2023.10.05.14.27.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 14:27:08 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v5 07/10] drm/msm/dpu: drop DPU_HW_SUBBLK_INFO macro Date: Fri, 6 Oct 2023 00:27:00 +0300 Message-Id: <20231005212703.2400237-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231005212703.2400237-1-dmitry.baryshkov@linaro.org> References: <20231005212703.2400237-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As the subblock info is now mostly gone, inline and drop the macro DPU_HW_SUBBLK_INFO. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 40 ++++++++++--------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 19ab36ae6765..fc5027b0123a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -252,49 +252,51 @@ enum { u32 len; \ unsigned long features -/** - * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU - * @name: string name for debug purposes - * @base: offset of this sub-block relative to the block - * offset - * @len register block length of this sub-block - */ -#define DPU_HW_SUBBLK_INFO \ - char name[DPU_HW_BLK_NAME_LEN]; \ - u32 base; \ - u32 len - /** * struct dpu_scaler_blk: Scaler information - * @info: HW register and features supported by this sub-blk + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block * @version: qseed block revision, on QSEED3+ platforms this is the value of * scaler_blk.base + QSEED3_HW_VERSION registers. */ struct dpu_scaler_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; u32 version; }; struct dpu_csc_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; }; /** * struct dpu_pp_blk : Pixel processing sub-blk information - * @info: HW register and features supported by this sub-blk + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block * @version: HW Algorithm version */ struct dpu_pp_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; u32 version; }; /** * struct dpu_dsc_blk - DSC Encoder sub-blk information - * @info: HW register and features supported by this sub-blk + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block */ struct dpu_dsc_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; }; /**