From patchwork Fri Oct 6 13:14:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 730413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09A98E81DF4 for ; Fri, 6 Oct 2023 13:15:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232340AbjJFNPC (ORCPT ); Fri, 6 Oct 2023 09:15:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232342AbjJFNPB (ORCPT ); Fri, 6 Oct 2023 09:15:01 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4CBE9F for ; Fri, 6 Oct 2023 06:14:59 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-5041d6d8b10so2743162e87.2 for ; Fri, 06 Oct 2023 06:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696598098; x=1697202898; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2hPtVzzZO9pBznL56T6VYtPDn+5rPWC88sELbHece2w=; b=WmFKfdunf/tnHQw6wmPPGlH+G2vE55YSCg8kR40cPj/WAdfjk1jzf+HyhfLt2IlkJp YGzICOOvGa440z1a55EjVHOItnqLXY73RH4xeEsHipMZp1vB3qCofZmJSl+dKCpHIpKM 2ChdNy3a//hEyFKmUp+Ct/CtmSLndCf3n9SvOxQHKfOyM7eENoN6FmC2Wro2gmmE8OJs Ab9kg8G1whTCabI86DK1sjZc9RXt7Y1el1AewPW6chzE1R32EBVABV4WmAYU7qCUE2XJ L4eBAdvSG4Tz3wH8vpAnbP0FkxzeGLhv0KhAcrBKcDDLuTOk79ozxWVLFZed0qb63svx +gwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696598098; x=1697202898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2hPtVzzZO9pBznL56T6VYtPDn+5rPWC88sELbHece2w=; b=S7IFIlNWYA3j3cry/8HAepW+96pbMMpfazAV8Td1M7LI6lLacSOMN8pV16xCjfAaZ5 gOrnuk/ns3dCzlCKiuNeBnsPGyQ/7qc50Ui733mNg6gm4FSCgaV+8bNvWIRW2JUabpcN UmFNEsBms4yzhCwYMJbxzSsi54sTTlWggNVFTj6gwzwAXuFVRzLH3GDf4dpHzY4nTFpn G39ahYuvRa2/k0a7Xbjyld/qePrZnbdrdZEVjbSsuoictu83Z5KrcI3XwGH0uvUe/DGO 8D0E8+kAYfMAFU8AkGsihakSUAgQJwmOaF7VkNjRVYhlpBt+QYROLV2lGkcwAZ6rehGf T9BA== X-Gm-Message-State: AOJu0YwQEMs3g3m0/MBsbYtPxsbx8WFoxHtY9sykqe1QwVXEzPuXJaZh 0yKI1PWhmqwuEp3Og7XFtcU2vQ== X-Google-Smtp-Source: AGHT+IEuGpQwunStAna/0FlSh6OhnJihhmODGHxngnzadM5uiN1WYGPNdJl/Uf8diykblnyD56W4qg== X-Received: by 2002:a05:6512:794:b0:500:7cab:efc3 with SMTP id x20-20020a056512079400b005007cabefc3mr5765830lfr.11.1696598097818; Fri, 06 Oct 2023 06:14:57 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id g9-20020a19ee09000000b004fbb011c9bcsm301285lfb.161.2023.10.06.06.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 06:14:57 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 07/10] drm/msm/dpu: drop DPU_HW_SUBBLK_INFO macro Date: Fri, 6 Oct 2023 16:14:47 +0300 Message-Id: <20231006131450.2436688-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231006131450.2436688-1-dmitry.baryshkov@linaro.org> References: <20231006131450.2436688-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As the subblock info is now mostly gone, inline and drop the macro DPU_HW_SUBBLK_INFO. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 40 ++++++++++--------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 19ab36ae6765..fc5027b0123a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -252,49 +252,51 @@ enum { u32 len; \ unsigned long features -/** - * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU - * @name: string name for debug purposes - * @base: offset of this sub-block relative to the block - * offset - * @len register block length of this sub-block - */ -#define DPU_HW_SUBBLK_INFO \ - char name[DPU_HW_BLK_NAME_LEN]; \ - u32 base; \ - u32 len - /** * struct dpu_scaler_blk: Scaler information - * @info: HW register and features supported by this sub-blk + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block * @version: qseed block revision, on QSEED3+ platforms this is the value of * scaler_blk.base + QSEED3_HW_VERSION registers. */ struct dpu_scaler_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; u32 version; }; struct dpu_csc_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; }; /** * struct dpu_pp_blk : Pixel processing sub-blk information - * @info: HW register and features supported by this sub-blk + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block * @version: HW Algorithm version */ struct dpu_pp_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; u32 version; }; /** * struct dpu_dsc_blk - DSC Encoder sub-blk information - * @info: HW register and features supported by this sub-blk + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block */ struct dpu_dsc_blk { - DPU_HW_SUBBLK_INFO; + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; }; /**