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([178.197.218.126]) by smtp.gmail.com with ESMTPSA id c64-20020a509fc6000000b0053ebafe7a60sm4743875edf.59.2023.10.19.08.36.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 08:36:01 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Banajit Goswami , Jaroslav Kysela , Takashi Iwai , linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] ASoC: qcom: Add support for WSA2 LPASS Date: Thu, 19 Oct 2023 17:35:41 +0200 Message-Id: <20231019153541.49753-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019153541.49753-1-krzysztof.kozlowski@linaro.org> References: <20231019153541.49753-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Qualcomm WSA2 LPASS (Low Power Audio SubSystem) audio ports to several Qualcomm ADSP drivers: Q6APM LPASS DAIs, Q6DSP LPASS ports and shared Q6DSP Soundwire code. Signed-off-by: Krzysztof Kozlowski --- sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 5 +++++ sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 6 ++++++ sound/soc/qcom/sdw.c | 5 +++++ 3 files changed, 16 insertions(+) diff --git a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c index c5e065a21e27..2ae10f9dc78e 100644 --- a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c +++ b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c @@ -36,6 +36,9 @@ static int q6dma_set_channel_map(struct snd_soc_dai *dai, case WSA_CODEC_DMA_TX_0: case WSA_CODEC_DMA_TX_1: case WSA_CODEC_DMA_TX_2: + case WSA2_CODEC_DMA_TX_0: + case WSA2_CODEC_DMA_TX_1: + case WSA2_CODEC_DMA_TX_2: case VA_CODEC_DMA_TX_0: case VA_CODEC_DMA_TX_1: case VA_CODEC_DMA_TX_2: @@ -60,6 +63,8 @@ static int q6dma_set_channel_map(struct snd_soc_dai *dai, break; case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: + case WSA2_CODEC_DMA_RX_0: + case WSA2_CODEC_DMA_RX_1: case RX_CODEC_DMA_RX_0: case RX_CODEC_DMA_RX_1: case RX_CODEC_DMA_RX_2: diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index 4919001de08b..a6502884531d 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -557,6 +557,11 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1), Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1), Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2), + Q6AFE_CDC_DMA_RX_DAI(WSA2_CODEC_DMA_RX_0), + Q6AFE_CDC_DMA_TX_DAI(WSA2_CODEC_DMA_TX_0), + Q6AFE_CDC_DMA_RX_DAI(WSA2_CODEC_DMA_RX_1), + Q6AFE_CDC_DMA_TX_DAI(WSA2_CODEC_DMA_TX_1), + Q6AFE_CDC_DMA_TX_DAI(WSA2_CODEC_DMA_TX_2), Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0), Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1), Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_2), @@ -622,6 +627,7 @@ struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev, q6dsp_audio_fe_dais[i].ops = cfg->q6tdm_ops; break; case WSA_CODEC_DMA_RX_0 ... RX_CODEC_DMA_RX_7: + case WSA2_CODEC_DMA_RX_0 ... WSA2_CODEC_DMA_TX_2: q6dsp_audio_fe_dais[i].ops = cfg->q6dma_ops; break; default: diff --git a/sound/soc/qcom/sdw.c b/sound/soc/qcom/sdw.c index 1a41419c7eb8..612865b26f88 100644 --- a/sound/soc/qcom/sdw.c +++ b/sound/soc/qcom/sdw.c @@ -21,6 +21,8 @@ int qcom_snd_sdw_prepare(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: + case WSA2_CODEC_DMA_RX_0: + case WSA2_CODEC_DMA_RX_1: case RX_CODEC_DMA_RX_0: case RX_CODEC_DMA_RX_1: case TX_CODEC_DMA_TX_0: @@ -70,6 +72,7 @@ int qcom_snd_sdw_hw_params(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case WSA_CODEC_DMA_RX_0: + case WSA2_CODEC_DMA_RX_0: case RX_CODEC_DMA_RX_0: case RX_CODEC_DMA_RX_1: case TX_CODEC_DMA_TX_0: @@ -98,6 +101,8 @@ int qcom_snd_sdw_hw_free(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: + case WSA2_CODEC_DMA_RX_0: + case WSA2_CODEC_DMA_RX_1: case RX_CODEC_DMA_RX_0: case RX_CODEC_DMA_RX_1: case TX_CODEC_DMA_TX_0: