From patchwork Tue Dec 12 13:32:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Om Prakash Singh X-Patchwork-Id: 753157 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PLRdA2CF" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C228ED; Tue, 12 Dec 2023 05:33:31 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BCCZ8Rs017060; Tue, 12 Dec 2023 13:33:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=oVr8YV32TzNcJ7vwe+veBUyJhWy6NHBxNHXdbsJpJjU=; b=PL RdA2CFaFkyD6ZClv0FLo96Uc6gdNPkWuVrrw0Xx+5KdyD+L+gNrmsewHoLE2VJf+ a6gkDDgWSqjVjS3K3Mn2WZ/90J1q7s2dVv38O6bqeil2t1dgUFQWXd39Nt3+9G0A bF/5l66VjItqpK+UHlA8LRtca1E9nXjyzE0oDLIkwcL1EsDczbXbpF2JBHc4hIPV 7woWITOnEP6aKSG1Do8oBFUpfUPuiB7Q4dHvM4M+nj4m4ZZnTiO8aA6x0qb4DrNI vSA0JCfNlVaTv7fb3oMvV7py7PxOgQNMvSxoPSBCZVEIXnlIRwjEN49aORIC7AjI 6FBJbEOkGCFajL18l1iw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uxepkhc2a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 13:33:24 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BCDXNMQ007444 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 13:33:23 GMT Received: from hu-omprsing-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 12 Dec 2023 05:33:18 -0800 From: Om Prakash Singh To: CC: , , , , , , , , , , , , , , Subject: [PATCH V2 2/2] arm64: dts: qcom: sc7280: add QCrypto nodes Date: Tue, 12 Dec 2023 19:02:47 +0530 Message-ID: <20231212133247.1366698-3-quic_omprsing@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212133247.1366698-1-quic_omprsing@quicinc.com> References: <20231212133247.1366698-1-quic_omprsing@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Z8eSrau29sVmXH87K2oQWUyN1hU0cXQA X-Proofpoint-ORIG-GUID: Z8eSrau29sVmXH87K2oQWUyN1hU0cXQA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=895 spamscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312120104 Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Om Prakash Singh --- Changes in V2: - Update DT node sequence as per register ascending order - Fix DT node properties as per convention arch/arm64/boot/dts/qcom/sc7280.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 66f1eb83cca7..7b705df21f4e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2272,6 +2272,28 @@ ipa: ipa@1e40000 { status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x4e4 0x0011>, + <&apps_smmu 0x4e6 0x0011>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x4e4 0x0011>, + <&apps_smmu 0x4e4 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>;