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[178.235.179.28]) by smtp.gmail.com with ESMTPSA id fb20-20020a1709073a1400b00a26a061ae1esm6854252ejc.97.2023.12.27.14.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:28:32 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:28:26 +0100 Subject: [PATCH 1/3] arm64: dts: qcom: sc8280xp: Fix PCIe PHY power-domains Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231227-topic-8280_pcie_dts-v1-1-13d12b1698ff@linaro.org> References: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> In-Reply-To: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Johan Hovold Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703716109; l=2255; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=kMvRAvWfpP/DEkU3LU/WsYqL/aUkUp2LCfdAhZy7cI4=; b=on07lEwMe5d6HDnWJbd3ihCw4sDHjf6qoR6QPRX9iQ0Vnh0ruqYLUNj+EZc5bK1Y5UyUQikEE 6Fwi+MxoF+pDhYo9Felu72ulAdl/i+cto7szIDueMCbObm95l0u4r++ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators. Fix the power-domains assignment to stop potentially toggling the GDSC unnecessarily. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..72c5818b67f2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1797,7 +1797,7 @@ pcie4_phy: phy@1c06000 { assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_4_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_4_PHY_BCR>; reset-names = "phy"; @@ -1895,7 +1895,7 @@ pcie3b_phy: phy@1c0e000 { assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_3B_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_3B_PHY_BCR>; reset-names = "phy"; @@ -1994,7 +1994,7 @@ pcie3a_phy: phy@1c14000 { assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_3A_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_3A_PHY_BCR>; reset-names = "phy"; @@ -2094,7 +2094,7 @@ pcie2b_phy: phy@1c1e000 { assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_2B_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_2B_PHY_BCR>; reset-names = "phy"; @@ -2193,7 +2193,7 @@ pcie2a_phy: phy@1c24000 { assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_2A_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_2A_PHY_BCR>; reset-names = "phy";