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[178.235.179.28]) by smtp.gmail.com with ESMTPSA id fb20-20020a1709073a1400b00a26a061ae1esm6854252ejc.97.2023.12.27.14.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:28:34 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:28:28 +0100 Subject: [PATCH 3/3] arm64: dts: qcom: sc8280xp-crd: Add PCIe CLKREQ# sleep state Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231227-topic-8280_pcie_dts-v1-3-13d12b1698ff@linaro.org> References: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> In-Reply-To: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Johan Hovold Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703716109; l=3813; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wNNlr9q+wppYjS6msbjrsQS3RolKg1AY+hca/Z4U7jI=; b=qvq7xUeQksr7Wqrk/el2CPvZx9ZDK+mjMvIO6NWtJvxBebD4JEsJG5MRUsJQywBQ4No1d6d8u drvcG+ZKWDZB+kZyoUxuGcD2bA1JsYUTbQtbPJGX9VjDZf0OxLFEE2c X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The CLKREQ pin should not be muxed to its active function when the RC is asleep. Add the missing pin sleep states to resolve that. Fixes: d907fe5acbf1 ("arm64: dts: qcom: sc8280xp-crd: enable WiFi controller") Fixes: 17e2ccaf65d1 ("arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem") Fixes: 6a1ec5eca73c ("arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 78 ++++++++++++++++++++----------- 1 file changed, 51 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index ffc4406422ae..58c0c2d10cb3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -530,8 +530,9 @@ &pcie2a { vddpe-3v3-supply = <&vreg_nvme>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2a_default>; + pinctrl-0 = <&pcie2a_default>, <&pcie2a_clkreq_default>; + pinctrl-1 = <&pcie2a_default>, <&pcie2a_clkreq_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -549,8 +550,9 @@ &pcie3a { vddpe-3v3-supply = <&vreg_wwan>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3a_default>; + pinctrl-0 = <&pcie3a_default>, <&pcie3a_clkreq_default>; + pinctrl-1 = <&pcie3a_default>, <&pcie3a_clkreq_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -568,8 +570,9 @@ &pcie4 { vddpe-3v3-supply = <&vreg_wlan>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie4_default>; + pinctrl-0 = <&pcie4_default>, <&pcie4_clkreq_default>; + pinctrl-1 = <&pcie4_default>, <&pcie4_clkreq_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -835,13 +838,6 @@ nvme_reg_en: nvme-reg-en-state { }; pcie2a_default: pcie2a-default-state { - clkreq-n-pins { - pins = "gpio142"; - function = "pcie2a_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - perst-n-pins { pins = "gpio143"; function = "gpio"; @@ -857,14 +853,21 @@ wake-n-pins { }; }; - pcie3a_default: pcie3a-default-state { - clkreq-n-pins { - pins = "gpio150"; - function = "pcie3a_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; + pcie2a_clkreq_default: pcie2a-clkreq-default-state { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie2a_clkreq_sleep: pcie2a-clkreq-sleep-state { + pins = "gpio142"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + pcie3a_default: pcie3a-default-state { perst-n-pins { pins = "gpio151"; function = "gpio"; @@ -880,14 +883,21 @@ wake-n-pins { }; }; - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio140"; - function = "pcie4_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; + pcie3a_clkreq_default: pcie3a-clkreq-default-state { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + pcie3a_clkreq_sleep: pcie3a-clkreq-sleep-state { + pins = "gpio150"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie4_default: pcie4-default-state { perst-n-pins { pins = "gpio141"; function = "gpio"; @@ -903,6 +913,20 @@ wake-n-pins { }; }; + pcie4_clkreq_default: pcie4-clkreq-default-state { + pins = "gpio140"; + function = "pcie4_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie4_clkreq_sleep: pcie4-clkreq-sleep-state { + pins = "gpio140"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + sdc2_default_state: sdc2-default-state { clk-pins { pins = "sdc2_clk";