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Wed, 13 Mar 2024 18:10:46 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id u19-20020a2e91d3000000b002d2ab6ae675sm48917ljg.137.2024.03.13.18.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 18:10:46 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 14 Mar 2024 03:10:42 +0200 Subject: [PATCH v3 2/5] drm/msm/dpu: core_perf: extract bandwidth aggregation function Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240314-dpu-perf-rework-v3-2-79fa4e065574@linaro.org> References: <20240314-dpu-perf-rework-v3-0-79fa4e065574@linaro.org> In-Reply-To: <20240314-dpu-perf-rework-v3-0-79fa4e065574@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2547; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=XB5qQZ6AM1gMdqH09M2m8W3Q7FcCw/TC5ffKreIP0Lc=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+onv0kXr8re+i35+SlTdqBy1spZr5luMYQ+snYTuNj6O 6JZfClnJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmkqbI/ovJbPuPd+LrnBLP Tzjj+pppSZDAq3k2HdHLK9qCywxrw9/c6V5y+t237E2zk/2+xlQpRP5e/OeBUA1v0IEpz1feM4h Z0R9XlnT6WMya/UpCbr7JgUZyu1Vsi8sXZib8047gDkg6qL4pdXlnwIOde01Xzlg+02oh27aUe4 b7uqYtEyh+v8aSyYHbS2We+vwJ3HosssyhCXUZH0z/Jkm0q7PtrHoZ773c8ADLA8kbp45YF0XUH Gwp0GNJdcn9u9BOVb3z/6f+O7ZzjFIu2QpM+CKa1md/rLSNaVFz3mnrHfxSCVHuJWzHygWzAo+J Razje3jyZcabDgb/JtE3vgkf/eR+typM5tRJqTm8aW4mAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In preparation to refactoring the dpu_core_perf debugfs interface, extract the bandwidth aggregation function from _dpu_core_perf_crtc_update_bus(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 45 +++++++++++++++------------ 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 68fae048a9a8..87b892069526 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -204,36 +204,41 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, return 0; } -static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, - struct drm_crtc *crtc) +static void dpu_core_perf_aggregate(struct drm_device *ddev, + enum dpu_crtc_client_type curr_client_type, + struct dpu_core_perf_params *perf) { - struct dpu_core_perf_params perf = { 0 }; - enum dpu_crtc_client_type curr_client_type - = dpu_crtc_get_client_type(crtc); - struct drm_crtc *tmp_crtc; struct dpu_crtc_state *dpu_cstate; - int i, ret = 0; - u64 avg_bw; - - if (!kms->num_paths) - return 0; + struct drm_crtc *tmp_crtc; - drm_for_each_crtc(tmp_crtc, crtc->dev) { + drm_for_each_crtc(tmp_crtc, ddev) { if (tmp_crtc->enabled && - curr_client_type == - dpu_crtc_get_client_type(tmp_crtc)) { + curr_client_type == dpu_crtc_get_client_type(tmp_crtc)) { dpu_cstate = to_dpu_crtc_state(tmp_crtc->state); - perf.max_per_pipe_ib = max(perf.max_per_pipe_ib, - dpu_cstate->new_perf.max_per_pipe_ib); + perf->max_per_pipe_ib = max(perf->max_per_pipe_ib, + dpu_cstate->new_perf.max_per_pipe_ib); - perf.bw_ctl += dpu_cstate->new_perf.bw_ctl; + perf->bw_ctl += dpu_cstate->new_perf.bw_ctl; - DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n", - tmp_crtc->base.id, - dpu_cstate->new_perf.bw_ctl, kms->num_paths); + DRM_DEBUG_ATOMIC("crtc=%d bw=%llu\n", + tmp_crtc->base.id, + dpu_cstate->new_perf.bw_ctl); } } +} + +static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, + struct drm_crtc *crtc) +{ + struct dpu_core_perf_params perf = { 0 }; + int i, ret = 0; + u64 avg_bw; + + if (!kms->num_paths) + return 0; + + dpu_core_perf_aggregate(crtc->dev, dpu_crtc_get_client_type(crtc), &perf); avg_bw = perf.bw_ctl; do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/