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a=openpgp-sha256; l=2999; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=vvIRN7ZBKQkTFnoIHX/YU42aYhGdx8c3NJ1/9vK0fxY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl8xaQGEjDj7V9nOkxQFG9KkzYhi7NMZ5fNY+WX /IyNnSDeqKJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfMWkAAKCRBVnxHm/pHO 9SzzB/0arBeoE0MTmN+C/QkksG5pbqe/k/wuAGkk2EO/pFuNZ20j163lecjuj4DJmfj5tmd3nQ1 sAaCxZ9VlIvHRrPnsmX/3tFhHtVqyxOKzTOuhfn5I81q5drJ/txgjtjvFbhRwQINFlCTKg/5/wU HyMA4ky1/DL4Qm9TiHqzEXMp5dgKj0vDTJ/mu1zOoZKcyyQl7eXfFxkLrS6tc1RzIk/k+bFJBdl S9R94h+EwTv/Ug+F3LeXIqmMfV2zi0wTgZiGX6RfxVWHy9E5V+uiRUk87DcZwAfnti60B6mP36m LGER5WQ8R6URgGjyDvuAN+Txnfrra4uwGHRL0AKboqnPQ40S X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 DWC specific start_link() and stop_link() callbacks are supposed to start and stop the link training of the PCIe bus. But the current endpoint implementation of this driver enables/disables the PERST# IRQ. Even though this is not causing any issues, this creates inconsistency among the EP controller drivers. So for the sake of consistency, let's just start/stop the link training in these callbacks. Also, PERST# IRQ is now enabled from the start itself, thus allowing the controller driver to initialize the registers when PERST# gets deasserted without waiting for the user intervention though configfs. Cc: Vidya Sagar Signed-off-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-tegra194.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 3e6e08b321fb..03d6f248bc6f 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -964,7 +964,11 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) bool retry = true; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { - enable_irq(pcie->pex_rst_irq); + /* Enable LTSSM */ + val = appl_readl(pcie, APPL_CTRL); + val |= APPL_CTRL_LTSSM_EN; + appl_writel(pcie, val, APPL_CTRL); + return 0; } @@ -1049,8 +1053,12 @@ static int tegra_pcie_dw_link_up(struct dw_pcie *pci) static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) { struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); + u32 val; - disable_irq(pcie->pex_rst_irq); + /* Disable LTSSM */ + val = appl_readl(pcie, APPL_CTRL); + val &= ~APPL_CTRL_LTSSM_EN; + appl_writel(pcie, val, APPL_CTRL); } static const struct dw_pcie_ops tegra_dw_pcie_ops = { @@ -1702,11 +1710,6 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) if (pcie->ep_state == EP_STATE_DISABLED) return; - /* Disable LTSSM */ - val = appl_readl(pcie, APPL_CTRL); - val &= ~APPL_CTRL_LTSSM_EN; - appl_writel(pcie, val, APPL_CTRL); - ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, ((val & APPL_DEBUG_LTSSM_STATE_MASK) >> APPL_DEBUG_LTSSM_STATE_SHIFT) == @@ -1913,11 +1916,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) appl_writel(pcie, val, APPL_LTR_MSG_2); } - /* Enable LTSSM */ - val = appl_readl(pcie, APPL_CTRL); - val |= APPL_CTRL_LTSSM_EN; - appl_writel(pcie, val, APPL_CTRL); - pcie->ep_state = EP_STATE_ENABLED; dev_dbg(dev, "Initialization of endpoint is completed\n"); @@ -2060,8 +2058,6 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, return -ENOMEM; } - irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); - pcie->ep_state = EP_STATE_DISABLED; ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,