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Fri, 29 Mar 2024 21:54:03 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 29 Mar 2024 14:54:00 -0700 From: Unnathi Chalicheemala Date: Fri, 29 Mar 2024 14:53:40 -0700 Subject: [PATCH v4 1/5] dt-bindings: arm: msm: Add llcc Broadcast_AND register Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240329-llcc-broadcast-and-v4-1-107c76fd8ceb@quicinc.com> References: <20240329-llcc-broadcast-and-v4-0-107c76fd8ceb@quicinc.com> In-Reply-To: <20240329-llcc-broadcast-and-v4-0-107c76fd8ceb@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: , , , , Unnathi Chalicheemala X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1711749240; l=2507; i=quic_uchalich@quicinc.com; s=20240202; h=from:subject:message-id; bh=BkpAtmS8Rvug+lXoZodZdEE8Pzy5W8JODJH0waZXtNw=; b=2KwM/IX+8f15Jm2xFgS85uwI/Q0snyMdvCH3OZa8yLLpZJZOoi+FlaPQaVp4+grqR+O5whxZQ OQEq6cUXCqcAeDC31hkGoSe1ZI4wns9fKpqkZ3O2uK7G/xDu8EuySBz X-Developer-Key: i=quic_uchalich@quicinc.com; a=ed25519; pk=8n+IFmsCDcEIg91sUP/julv9kf7kmyIKT2sR+1yFd4A= X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: lr6KcWDfSQ4sQjBPHfhQuDNn2wW1eFi1 X-Proofpoint-ORIG-GUID: lr6KcWDfSQ4sQjBPHfhQuDNn2wW1eFi1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-29_13,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=957 impostorscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403290195 The LLCC block in SM8450, SM8550 and SM8650 have a new register space for Broadcast_AND region. This is used to check that all channels have bit set to "1", mainly in SCID activation/deactivation. Previously we were mapping only the Broadcast_OR region assuming there was only one broadcast register region. Now we also map Broadcast_AND region. Signed-off-by: Unnathi Chalicheemala --- .../devicetree/bindings/cache/qcom,llcc.yaml | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 07ccbda4a0ab..a6237028957f 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -141,8 +141,31 @@ allOf: - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: - qcom,sm8450-llcc - qcom,sm8550-llcc + - qcom,sm8650-llcc then: properties: reg: @@ -151,7 +174,8 @@ allOf: - description: LLCC1 base register region - description: LLCC2 base register region - description: LLCC3 base register region - - description: LLCC broadcast base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region reg-names: items: - const: llcc0_base @@ -159,6 +183,7 @@ allOf: - const: llcc2_base - const: llcc3_base - const: llcc_broadcast_base + - const: llcc_broadcast_and_base additionalProperties: false